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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-14 19:30:05 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:05 +0100 |
| commit | e489f87bc10e8912983d6ae2e1beadbde1d509f8 (patch) | |
| tree | e03550c10f6ec43fcbf3a7e8039531c6f98d4004 | |
| parent | clk: renesas: r8a779g0: Add ISP core clocks (diff) | |
| download | wireguard-linux-e489f87bc10e8912983d6ae2e1beadbde1d509f8.tar.xz wireguard-linux-e489f87bc10e8912983d6ae2e1beadbde1d509f8.zip | |
clk: renesas: r8a779h0: Add ISP core clocks
Add the ISP core module clock for Renesas R-Car V4M.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 607fa815b6c1..4c8052ac32df 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -171,6 +171,7 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { + DEF_MOD("isp0", 16, R8A779H0_CLK_S0D2_VIO), DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), |