diff options
| author |   Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> | 2023-07-17 15:04:59 +0300 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2023-08-21 14:11:51 -0500 |
| commit | 30de872537bda526664d7a20b646adfb3e7ce6e6 (patch) | |
| tree | e3f919e3b832782ae7a3eca37fa95852047a8886 | |
| parent | drm/radeon: Use RMW accessors for changing LNKCTL (diff) | |
| download | wireguard-linux-30de872537bda526664d7a20b646adfb3e7ce6e6.tar.xz wireguard-linux-30de872537bda526664d7a20b646adfb3e7ce6e6.zip | |
net/mlx5: Use RMW accessors for changing LNKCTL
Don't assume that only the driver would be accessing LNKCTL of the upstream
bridge. ASPM policy changes can trigger write to LNKCTL outside of driver's
control.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value.
Suggested-by: Lukas Wunner <lukas@wunner.de>
Fixes: eabe8e5e88f5 ("net/mlx5: Handle sync reset now event")
Link: https://lore.kernel.org/r/20230717120503.15276-8-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 4804990b7f22..99dcbd006357 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -384,16 +384,11 @@ static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) pci_cfg_access_lock(sdev); } /* PCI link toggle */ - err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16); - if (err) - return err; - reg16 |= PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err; msleep(500); - reg16 &= ~PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err; |