diff options
| author |   Wen He <wen.he_1@nxp.com> | 2019-10-14 15:13:27 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-10-28 21:48:02 +0800 |
| commit | 91035cb05fb2ae62000b085ab2257c5a3e087170 (patch) | |
| tree | 812b658ca930142baba08de2c3a469620180af10 | |
| parent | arm64: dts: imx8mq-evk: VDD_ARM power rail is always ON (diff) | |
| download | wireguard-linux-91035cb05fb2ae62000b085ab2257c5a3e087170.tar.xz wireguard-linux-91035cb05fb2ae62000b085ab2257c5a3e087170.zip | |
arm64: dts: ls1028a: Update #clock-cells of dpclk node
Update the property #clock-cells = <1> to #clock-cells = <0> of the
dpclk, since the Display output pixel clock driver provides single
clock output.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 51fa8f57fdac..616b150a15aa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -82,7 +82,7 @@ dpclk: clock-controller@f1f0000 { compatible = "fsl,ls1028a-plldig"; reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&osc_27m>; }; @@ -665,7 +665,7 @@ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>, + clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; |