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author | 2023-11-14 09:12:47 -0500 | |
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committer | 2023-12-12 15:45:08 -0800 | |
commit | c44714c35ff861d69db9c8bb4ae1347373f817f0 (patch) | |
tree | d205697cd3b35d5057aa67c690c019c322c6c140 | |
parent | riscv: hwprobe: export Zfh[min] ISA extensions (diff) | |
download | wireguard-linux-c44714c35ff861d69db9c8bb4ae1347373f817f0.tar.xz wireguard-linux-c44714c35ff861d69db9c8bb4ae1347373f817f0.zip |
dt-bindings: riscv: add Zfh[min] ISA extensions description
Add description of Zfh[min] ISA extensions[1].
Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-12-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to '')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index e845e461b6e1..f3c99e69619b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -214,6 +214,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("Update + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support for + 16-bit half-precision binary floating-point instructions, as ratified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as ratified |