diff options
| author |   Thierry Reding <treding@nvidia.com> | 2015-07-07 21:14:12 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:52 +0100 |
| commit | c4a27288520d35e7e6acc6e36fba4585e1bddde6 (patch) | |
| tree | 3036550e849bb0b7d7cdba87e12fb3911bc33cb0 | |
| parent | drm/tegra: dp: Set channel coding on link configuration (diff) | |
| download | wireguard-linux-c4a27288520d35e7e6acc6e36fba4585e1bddde6.tar.xz wireguard-linux-c4a27288520d35e7e6acc6e36fba4585e1bddde6.zip | |
drm/tegra: dp: Enable alternate scrambler reset when supported
If the sink is eDP and supports the alternate scrambler reset, enable
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index ca287b50fad8..638081b568f4 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -225,5 +225,12 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) if (err < 0) return err; + if (link->caps.alternate_scrambler_reset) { + err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, + DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); + if (err < 0) + return err; + } + return 0; } |