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| author |   Xiaolei Wang <xiaolei.wang@windriver.com> | 2023-07-26 15:57:47 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2023-07-30 21:45:24 +0800 |
| commit | 0a2b96e42a0284c4fc03022236f656a085ca714a (patch) | |
| tree | ced7b5e4e8e02bc3a3df2ef339d3e44ea7edfffa | |
| parent | arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration (diff) | |
| download | wireguard-linux-0a2b96e42a0284c4fc03022236f656a085ca714a.tar.xz wireguard-linux-0a2b96e42a0284c4fc03022236f656a085ca714a.zip | |
ARM: dts: imx: Set default tuning step for imx6sx usdhc
If the tuning step is not set, the tuning step is set to 1.
For some sd cards, the following Tuning timeout will occur.
Tuning failed, falling back to fixed sampling clock
So set the default tuning step. This refers to the NXP vendor's
commit below:
https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/
arch/arm/boot/dts/imx6sx.dtsi#L1108-L1109
Fixes: 1e336aa0c025 ("mmc: sdhci-esdhc-imx: correct the tuning start tap and step setting")
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 41c900929758..a05069d49cb8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -1009,6 +1009,8 @@ <&clks IMX6SX_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -1021,6 +1023,8 @@ <&clks IMX6SX_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -1033,6 +1037,8 @@ <&clks IMX6SX_CLK_USDHC3>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; |