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| author |   Thierry Reding <treding@nvidia.com> | 2018-02-05 14:31:27 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:44 +0100 |
| commit | 0fa5c1bdd2f7dfc3cc5a9b22470fb4ffdbe22272 (patch) | |
| tree | fefdb9693b94eaded4a51a169439b7b7a13c66bf | |
| parent | drm/tegra: dpaux: Parameterize CMH, DRVZ and DRVI (diff) | |
| download | wireguard-linux-0fa5c1bdd2f7dfc3cc5a9b22470fb4ffdbe22272.tar.xz wireguard-linux-0fa5c1bdd2f7dfc3cc5a9b22470fb4ffdbe22272.zip | |
drm/tegra: Add missing kerneldoc for struct drm_dp_link
The drm_dp_link structure tracks capabilities on the DP link. Add some
kerneldoc to explain what each of its fields means.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 88842fd25abf..1cf252e7309a 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -11,6 +11,13 @@ struct drm_dp_aux; #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +/** + * struct drm_dp_link - DP link capabilities + * @revision: DP specification revision supported on the link + * @rate: maximum clock rate supported on the link + * @num_lanes: maximum number of lanes supported on the link + * @capabilities: bitmask of capabilities supported on the link + */ struct drm_dp_link { unsigned char revision; unsigned int rate; |