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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-01-23 16:29:21 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:28 -0800 |
| commit | 0ff0af18216436d0151af4e410400c7a19ca9437 (patch) | |
| tree | b4982719f3e547332a73664764d0318ea4011892 | |
| parent | cxl: Introduce module_cxl_driver (diff) | |
| download | wireguard-linux-0ff0af18216436d0151af4e410400c7a19ca9437.tar.xz wireguard-linux-0ff0af18216436d0151af4e410400c7a19ca9437.zip | |
cxl/core/port: Rename bus.c to port.c
Given it is dominated by port infrastructure, and will only acquire
more, rename bus.c to port.c.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164298416136.3018233.15442880970000855425.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| -rw-r--r-- | Documentation/driver-api/cxl/memory-devices.rst | 4 | ||||
| -rw-r--r-- | drivers/cxl/core/Makefile | 2 | ||||
| -rw-r--r-- | drivers/cxl/core/port.c (renamed from drivers/cxl/core/bus.c) | 0 | ||||
| -rw-r--r-- | tools/testing/cxl/Kbuild | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst index 3b8f41395f6b..c8f7a16cd0e3 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -36,10 +36,10 @@ CXL Core .. kernel-doc:: drivers/cxl/cxl.h :internal: -.. kernel-doc:: drivers/cxl/core/bus.c +.. kernel-doc:: drivers/cxl/core/port.c :doc: cxl core -.. kernel-doc:: drivers/cxl/core/bus.c +.. kernel-doc:: drivers/cxl/core/port.c :identifiers: .. kernel-doc:: drivers/cxl/core/pmem.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 40ab50318daf..a90202ac88d2 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -2,7 +2,7 @@ obj-$(CONFIG_CXL_BUS) += cxl_core.o ccflags-y += -I$(srctree)/drivers/cxl -cxl_core-y := bus.o +cxl_core-y := port.o cxl_core-y += pmem.o cxl_core-y += regs.o cxl_core-y += memdev.o diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/port.c index 3f9b98ecd18b..3f9b98ecd18b 100644 --- a/drivers/cxl/core/bus.c +++ b/drivers/cxl/core/port.c diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 1acdf2fc31c5..3299fb0977b2 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -25,7 +25,7 @@ cxl_pmem-y += config_check.o obj-m += cxl_core.o -cxl_core-y := $(CXL_CORE_SRC)/bus.o +cxl_core-y := $(CXL_CORE_SRC)/port.o cxl_core-y += $(CXL_CORE_SRC)/pmem.o cxl_core-y += $(CXL_CORE_SRC)/regs.o cxl_core-y += $(CXL_CORE_SRC)/memdev.o |