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authorJerome Brunet <jbrunet@baylibre.com>2019-06-11 11:26:09 +0200
committerJerome Brunet <jbrunet@baylibre.com>2019-06-11 11:26:09 +0200
commit1360952c96ccd394c118c66b968acd534b189e27 (patch)
tree3b2bc7a7f8ca39c5c45aa5804977d4fde89fdb22
parentclk: meson-g12a: add temperature sensor clocks (diff)
parentdt-bindings: clk: meson: add g12b periph clock controller bindings (diff)
downloadwireguard-linux-1360952c96ccd394c118c66b968acd534b189e27.tar.xz
wireguard-linux-1360952c96ccd394c118c66b968acd534b189e27.zip
Merge branch 'v5.3/dt' into v5.3/drivers
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 5c8b105be4d6..6eaa52092313 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -10,6 +10,7 @@ Required Properties:
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
+ "amlogic,g12b-clkc" for G12B SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal