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| author |   Leo Liu <leo.liu@amd.com> | 2020-01-20 10:07:40 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:10 -0400 |
| commit | 14765e9c225eb4416d2584697d443a264fbd4806 (patch) | |
| tree | 2d630792b1b274c986f30173c023e5185a950fb5 | |
| parent | drm/amdgpu: open GFX clock gating for sienna_cichlid (diff) | |
| download | wireguard-linux-14765e9c225eb4416d2584697d443a264fbd4806.tar.xz wireguard-linux-14765e9c225eb4416d2584697d443a264fbd4806.zip | |
drm/amdgpu: change the offset for VCN FW cache window
The signed header is added
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 011edbdd4e55..371c70a1e611 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -356,11 +356,8 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, upper_32_bits(adev->vcn.inst[inst].gpu_addr)); offset = size; - /* No signed header for now from firmware WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); - */ - WREG32_SOC15(UVD, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); } WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); |