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| author |   Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2023-07-25 14:00:02 +0530 |
|---|---|---|
| committer |   Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2023-07-27 18:09:12 +0530 |
| commit | 14c8fca214a27e24f033fe906191651ffe601074 (patch) | |
| tree | e269af050d04153b64df97754e2f42cbae39314c | |
| parent | drm/i915/color: Upscale degamma values for MTL (diff) | |
| download | wireguard-linux-14c8fca214a27e24f033fe906191651ffe601074.tar.xz wireguard-linux-14c8fca214a27e24f033fe906191651ffe601074.zip | |
drm/i915/color: Downscale degamma lut values read from hardware
For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.
v2: Add helper function to downscale values (Jani)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230725083002.3779717-3-chaitanya.kumar.borah@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_color.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 211b7fce1b27..454607b4a02a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3456,6 +3456,14 @@ static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc) for (i = 0; i < lut_size; i++) { u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe)); + /* + * For MTL and beyond, convert back the 24 bit lut values + * read from HW to 16 bit values to maintain parity with + * userspace values + */ + if (DISPLAY_VER(dev_priv) >= 14) + val = change_lut_val_precision(val, 16, 24); + lut[i].red = val; lut[i].green = val; lut[i].blue = val; |