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| author |   Yangyu Chen <cyy@cyyself.name> | 2024-07-30 00:28:05 +0000 |
|---|---|---|
| committer |   Yixun Lan <dlan@gentoo.org> | 2025-01-17 07:53:50 +0800 |
| commit | 16c9147e6a6c6342f4b1f9909b8f914f6e4adcab (patch) | |
| tree | 9ad2e536dbb3162d10bc6ef2c10ef0b320e5a94e | |
| parent | MAINTAINERS: setup support for SpacemiT SoC tree (diff) | |
| download | wireguard-linux-16c9147e6a6c6342f4b1f9909b8f914f6e4adcab.tar.xz wireguard-linux-16c9147e6a6c6342f4b1f9909b8f914f6e4adcab.zip | |
dt-bindings: riscv: Add SpacemiT X60 compatibles
The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.
Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 8edc8261241a..acb5b9ba6f04 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -46,6 +46,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x60 - thead,c906 - thead,c908 - thead,c910 |