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| author |   Changbin Du <changbin.du@intel.com> | 2017-06-06 15:56:14 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-06-08 13:59:21 +0800 |
| commit | 178cd160c6652f57571ba3dc0a9091a1f41d9bc8 (patch) | |
| tree | e02e5bbfa5e745c1e1a060fa4837253304de95fc | |
| parent | drm/i915/gvt: Add helper for tuning MMIO hash table (diff) | |
| download | wireguard-linux-178cd160c6652f57571ba3dc0a9091a1f41d9bc8.tar.xz wireguard-linux-178cd160c6652f57571ba3dc0a9091a1f41d9bc8.zip | |
drm/i915/gvt: Tuning the size of MMIO hash lookup table to 2048
On Skylake platform, The traced virtual mmio registers are up to 2039.
So tuning the hash table size to improve lookup performance.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index ffb9ebbbcf5a..3a74e79eac2f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -195,7 +195,7 @@ struct intel_gvt_fence { unsigned long vgpu_allocated_fence_num; }; -#define INTEL_GVT_MMIO_HASH_BITS 9 +#define INTEL_GVT_MMIO_HASH_BITS 11 struct intel_gvt_mmio { u8 *mmio_attribute; |