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author | 2025-02-18 08:41:50 +0100 | |
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committer | 2025-02-25 08:33:00 +0800 | |
commit | 1fcb3dc13447b944ca3892afb0ddbe4a8863a361 (patch) | |
tree | 784cd371a56aa31c8e17cfc4bc3b62e8248c2064 | |
parent | arm64: dts: imx8mm-phygate-tauri-l: Set RTC as wakeup-source (diff) | |
download | wireguard-linux-1fcb3dc13447b944ca3892afb0ddbe4a8863a361.tar.xz wireguard-linux-1fcb3dc13447b944ca3892afb0ddbe4a8863a361.zip |
arm64: dts: imx8mm: move bulk of rtc properties to carrierboards
Move properties from SoM's dtsi to carrierboard's dts as they are
actually defined by the carrier board design.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
3 files changed, 20 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 7aaf705c7e47..17e5dd40b5d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -221,6 +221,10 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; wakeup-source; @@ -410,6 +414,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index cced82226c6d..672baba4c8d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -301,10 +301,6 @@ /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; reg = <0x52>; }; }; @@ -377,12 +373,6 @@ >; }; - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - pinctrl_sn65dsi83: sn65dsi83grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index c9bf4ac254bb..755cf9cacd22 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -215,6 +215,10 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; wakeup-source; @@ -395,6 +399,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tempsense: tempsensegrp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 |