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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-07-07 15:20:42 +0100 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2022-07-08 09:09:46 +0200 |
| commit | 2058dc831ff82eb8e93e882efd1ca964bd8a74c8 (patch) | |
| tree | ee99cf4bb0d1fa249062ba0c70ac18f984435b6d | |
| parent | MAINTAINERS: mark ARM/PALM TREO SUPPORT orphan (diff) | |
| download | wireguard-linux-2058dc831ff82eb8e93e882efd1ca964bd8a74c8.tar.xz wireguard-linux-2058dc831ff82eb8e93e882efd1ca964bd8a74c8.zip | |
MAINTAINERS: add polarfire rng, pci and clock drivers
Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220707142041.4096246-1-conor.dooley@microchip.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | MAINTAINERS | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e20124db1381..7a3eab75f967 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17202,12 +17202,15 @@ N: riscv K: riscv RISC-V/MICROCHIP POLARFIRE SOC SUPPORT -M: Lewis Hanly <lewis.hanly@microchip.com> M: Conor Dooley <conor.dooley@microchip.com> +M: Daire McNamara <daire.mcnamara@microchip.com> L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/boot/dts/microchip/ +F: drivers/char/hw_random/mpfs-rng.c +F: drivers/clk/microchip/clk-mpfs.c F: drivers/mailbox/mailbox-mpfs.c +F: drivers/pci/controller/pcie-microchip-host.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h |