diff options
| author |   Charlene Liu <Charlene.Liu@amd.com> | 2025-03-07 18:24:56 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-03-18 14:03:47 -0400 |
| commit | 20c13ca5ba84e68046c8ce6d93729b46e591d87b (patch) | |
| tree | c809348d408f5eb9e7866b43445af4102a295b03 | |
| parent | drm/amd/display: Fix incorrect fw_state address in dmub_srv (diff) | |
| download | wireguard-linux-20c13ca5ba84e68046c8ce6d93729b46e591d87b.tar.xz wireguard-linux-20c13ca5ba84e68046c8ce6d93729b46e591d87b.zip | |
drm/amd/display: Update static soc table
[WHY]
Update the static soc table dcn3_5_soc.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index e8efffcc69a1..92f0a099d089 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -159,7 +159,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { .dppclk_mhz = 1200.0, .phyclk_mhz = 810.0, .phyclk_d18_mhz = 667.0, - .dscclk_mhz = 417.0, + .dscclk_mhz = 400.0, .dtbclk_mhz = 600.0, }, }, |