diff options
| author |   Frank Li <Frank.Li@nxp.com> | 2024-10-25 18:08:08 -0400 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2024-11-04 16:46:32 +0800 |
| commit | 2e3c8cffb8167ff732db477a51ea52f315594100 (patch) | |
| tree | 9c3d55a3f9c5b77f60a21c3b651206aa1f827942 | |
| parent | arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and output-high in GPIO (diff) | |
| download | wireguard-linux-2e3c8cffb8167ff732db477a51ea52f315594100.tar.xz wireguard-linux-2e3c8cffb8167ff732db477a51ea52f315594100.zip | |
arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0
Update clock settings to use the macro IMX_LPCG_CLK_0 instead of the
hardcoded value 0. The first argument of lpcg is indices, not index.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 317e8c8319f2..be79c793213a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -249,8 +249,8 @@ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&esai0_lpcg 0>; - assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + <&esai0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-0 = <&pinctrl_esai0>; pinctrl-names = "default"; @@ -430,12 +430,12 @@ cs42888: audio-codec@48 { compatible = "cirrus,cs42888"; reg = <0x48>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&mclkout0_lpcg 0>; + <&mclkout0_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>; VA-supply = <®_audio>; |