diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2025-03-27 09:01:37 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-03-27 09:01:37 -0700 |
| commit | 2f24482304ebd32c5aa374f31465b9941a860b92 (patch) | |
| tree | 80cd19b665a1523b1114fe717e96e5eb676cc5e0 | |
| parent | Merge tag 'net-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next (diff) | |
| parent | Merge tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt (diff) | |
| download | wireguard-linux-2f24482304ebd32c5aa374f31465b9941a860b92.tar.xz wireguard-linux-2f24482304ebd32c5aa374f31465b9941a860b92.zip | |
Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There is new support for additional on-chip devices on Apple,
Mediatek, Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and
Amlogic devices.
The Arm Morello reference platform gets a devicetree for booting in
normal aarch64 mode. The hardware supports experimental CHERI support,
which requires a modified kernel.
The AMD (formerly Xilinx) Versal NET SoC gets added, this is a
combined FPGA with Cortex-A78 CPUs in a SoC.
Six new ST STM32MP2 SoC variants are added. Like the earlier
STM32MP25, the MP211, MP213, MP215, MP231, MP233 and MP235 models are
based on one or two Cortex-A35 cores but each feature a different set
of I/O devices.
Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and GPU
cores
Apple T2 is the baseboard management controller on earlier Intel CPU
based Macs, with 16 models now gaining initial support.
All the above come with dts files for the reference boards. In
addition, these boards are added for the SoCs that are already
supported:
- The Milk-V Jupiter board based on SpacemiT K1/M1
- NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
- Three boards based on 32-bit stm32mp1
- 11 distinct board variants from Toradex and one from Variscite, all
based on i.MX6
- Google Pixel Pro 6 phone based on gs101 (Tensor)
- Three additional variants of the i.MX8MP based "Skov" board
- A second variant of the i.MX95 EVK board
- Two boards based on Renesas SoCs
- Four boards based the Rockchip RK35xx series, plus the RK3588 'MNT
Reform 2' laptop"
* tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (538 commits)
arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
arm64: dts: hi3660: Add property for fixing CPUIdle
arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
arm64: dts: marvell: Use preferred node names for "simple-bus"
arm64: dts: marvell: Drop unused CP11X_TYPE define
arm64: dts: marvell: Move arch timer and pmu nodes to top-level
arm64: dts: rockchip: Fix PWM pinctrl names
arm64: dts: rockchip: fix RK3576 SCMI clock IDs
dt-bindings: clock: rk3576: add SCMI clocks
arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
arm64: dts: amd/seattle: Move and simplify fixed clocks
arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
arm64: dts: rockchip: Add SDHCI controller for RK3528
arm64: dts: rockchip: Remove bluetooth node from rock-3a
arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
...
646 files changed, 35688 insertions, 2992 deletions
diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index dc9aab19ff11..da60e9de1cfb 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -57,6 +57,25 @@ description: | - iPad Pro (2nd Generation) (10.5 Inch) - iPad Pro (2nd Generation) (12.9 Inch) + Devices based on the "T2" SoC: + + - Apple T2 MacBookPro15,2 (j132) + - Apple T2 iMacPro1,1 (j137) + - Apple T2 MacBookAir8,2 (j140a) + - Apple T2 MacBookAir8,1 (j140k) + - Apple T2 MacBookPro16,1 (j152f) + - Apple T2 MacPro7,1 (j160) + - Apple T2 Macmini8,1 (j174) + - Apple T2 iMac20,1 (j185) + - Apple T2 iMac20,2 (j185f) + - Apple T2 MacBookPro15,4 (j213) + - Apple T2 MacBookPro16,2 (j214k) + - Apple T2 MacBookPro16,4 (j215) + - Apple T2 MacBookPro16,3 (j223) + - Apple T2 MacBookAir9,1 (j230k) + - Apple T2 MacBookPro15,1 (j680) + - Apple T2 MacBookPro15,3 (j780) + Devices based on the "A11" SoC: - iPhone 8 @@ -211,6 +230,28 @@ properties: - const: apple,t8011 - const: apple,arm-platform + - description: Apple T2 SoC based platforms + items: + - enum: + - apple,j132 # Apple T2 MacBookPro15,2 (j132) + - apple,j137 # Apple T2 iMacPro1,1 (j137) + - apple,j140a # Apple T2 MacBookAir8,2 (j140a) + - apple,j140k # Apple T2 MacBookAir8,1 (j140k) + - apple,j152f # Apple T2 MacBookPro16,1 (j152f) + - apple,j160 # Apple T2 MacPro7,1 (j160) + - apple,j174 # Apple T2 Macmini8,1 (j174) + - apple,j185 # Apple T2 iMac20,1 (j185) + - apple,j185f # Apple T2 iMac20,2 (j185f) + - apple,j213 # Apple T2 MacBookPro15,4 (j213) + - apple,j214k # Apple T2 MacBookPro16,2 (j214k) + - apple,j215 # Apple T2 MacBookPro16,4 (j215) + - apple,j223 # Apple T2 MacBookPro16,3 (j223) + - apple,j230k # Apple T2 MacBookAir9,1 (j230k) + - apple,j680 # Apple T2 MacBookPro15,1 (j680) + - apple,j780 # Apple T2 MacBookPro15,3 (j780) + - const: apple,t8012 + - const: apple,arm-platform + - description: Apple A11 SoC based platforms items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 673277a7a224..5001f4d5a0dc 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -22,6 +22,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr - apple,t8103-pmgr - apple,t8112-pmgr - apple,t6000-pmgr diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml new file mode 100644 index 000000000000..e843b97fa485 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino <vincenzo.frascino@arm.com> + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Platforms + items: + - enum: + - arm,morello-sdp + - arm,morello-fvp + - const: arm,morello + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e666b2a4dcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0db2cbd7891f..1b90870958a2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -97,6 +97,7 @@ properties: - i2se,duckbill - i2se,duckbill-2 - karo,tx28 # Ka-Ro electronics TX28 module + - lwn,imx28-btt3 - lwn,imx28-xea - msr,m28cu3 # M28 SoM with custom base board - schulercontrol,imx28-sps1 @@ -296,7 +297,6 @@ properties: - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - - toradex,apalis_imx6q # Apalis iMX6 Modules - udoo,imx6q-udoo # Udoo i.MX6 Quad Board - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard @@ -490,7 +490,6 @@ properties: - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - - toradex,colibri_imx6dl # Colibri iMX6 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -688,6 +687,12 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul + - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + items: + - const: variscite,mx6ulconcerto + - const: variscite,var-som-imx6ul + - const: fsl,imx6ul + - description: Kontron BL i.MX6UL (N631X S) Board items: - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board @@ -730,9 +735,6 @@ properties: - joz,jozacp # JOZ Access Point - kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules - uni-t,uti260b # UNI-T UTi260B Thermal Camera - const: fsl,imx6ull @@ -891,8 +893,6 @@ properties: - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi - - toradex,colibri-imx7d # Colibri iMX7D Module - - toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d @@ -962,9 +962,6 @@ properties: - innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm @@ -1098,12 +1095,12 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules + - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate + - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp @@ -1273,8 +1270,6 @@ properties: - enum: - fsl,imx8qm-mek # i.MX8QM MEK Board - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - - toradex,apalis-imx8 # Apalis iMX8 Modules - - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules - const: fsl,imx8qm - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules @@ -1355,6 +1350,7 @@ properties: - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - const: fsl,imx95 @@ -1435,7 +1431,6 @@ properties: - fsl,vf610-twr # VF610 Tower Board - lwn,bk4 # Liebherr BK4 controller - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board - - toradex,vf610-colibri_vf61 # Colibri VF61 Modules - const: fsl,vf610 - description: Toradex Colibri VF61 Module on Colibri Evaluation Board diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml index e20b5c9b16bc..99961e5282e5 100644 --- a/Documentation/devicetree/bindings/arm/google.yaml +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -34,10 +34,11 @@ properties: const: '/' compatible: oneOf: - - description: Google Pixel 6 / Oriole + - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: - google,gs101-oriole + - google,gs101-raven - const: google,gs101 # Bootloader requires empty ect node to be present diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml index 6905d29f3108..51e1386f0e01 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - cznic,turris-mox + - glinet,gl-mv1000 - globalscale,espressobin - marvell,armada-3720-db - methode,edpu diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 538d91be8857..4bc7454a5d3a 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -23,6 +23,9 @@ properties: - description: Armada 7040 SoC items: + - enum: + - globalscale,mochabin + - marvell,armada7040-db - const: marvell,armada7040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 @@ -35,10 +38,32 @@ properties: - description: Armada 8040 SoC items: + - enum: + - iei,puzzle-m801 + - marvell,armada8040-db + - solidrun,clearfog-gt-8k - const: marvell,armada8040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 + - description: Armada 8040 SoC MACCHIATOBin Boards + items: + - enum: + - marvell,armada8040-mcbin-doubleshot + - marvell,armada8040-mcbin-singleshot + - const: marvell,armada8040-mcbin + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8080 SoC + items: + - enum: + - marvell,armada-8080-db + - const: marvell,armada-8080 + - const: marvell,armada-ap810-octa + - const: marvell,armada-ap810 + - description: Armada CN9130 SoC with no external CP items: - const: marvell,cn9130 diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt deleted file mode 100644 index f3e9624534c6..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt +++ /dev/null @@ -1,15 +0,0 @@ -Marvell Armada 8KPlus Platforms Device Tree Bindings ----------------------------------------------------- - -Boards using a SoC of the Marvell Armada 8KP families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" - when the SoC being used is the Armada 8080 - -Example: - -compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810" diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 3ce34d68c213..108ae5e0185d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -414,6 +414,11 @@ properties: - const: mediatek,mt8365 - items: - enum: + - mediatek,mt8370-evk + - const: mediatek,mt8370 + - const: mediatek,mt8188 + - items: + - enum: - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 522a6f0450ea..650fb833d96e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -49,6 +49,11 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Ariaboard Photonicat + items: + - const: ariaboard,photonicat + - const: rockchip,rk3568 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 @@ -178,6 +183,13 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Firefly iCore-3588Q-based boards + items: + - enum: + - mntre,reform2-rcore + - const: firefly,icore-3588q + - const: rockchip,rk3588 + - description: Firefly Core-3588J-based boards items: - enum: @@ -236,6 +248,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly ROC-RK3576-PC + items: + - const: firefly,roc-rk3576-pc + - const: rockchip,rk3576 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc @@ -862,6 +879,11 @@ properties: - const: radxa,rock-4c-plus - const: rockchip,rk3399 + - description: Radxa ROCK 4D + items: + - const: radxa,rock-4d + - const: rockchip,rk3576 + - description: Radxa ROCK 4SE items: - const: radxa,rock-4se @@ -1136,11 +1158,12 @@ properties: - const: xunlong,orangepi-3b - const: rockchip,rk3566 - - description: Xunlong Orange Pi 5 Max/Plus + - description: Xunlong Orange Pi 5 Max/Plus/Ultra items: - enum: - xunlong,orangepi-5-max - xunlong,orangepi-5-plus + - xunlong,orangepi-5-ultra - const: rockchip,rk3588 - description: Xunlong Orange Pi R1 Plus / LTS diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index d083d8ad48b7..ed97652c8492 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -21,6 +21,8 @@ properties: - st,stm32f4-gcan - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg + - st,stm32mp21-syscfg + - st,stm32mp23-syscfg - st,stm32mp25-syscfg - const: syscon - items: diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b6c56d4ce6b9..5fee2f38ff25 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -51,9 +51,16 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP133 based Boards + items: + - enum: + - pri,prihmb # Priva E-Measuringbox board + - const: st,stm32mp133 + - description: ST STM32MP151 based Boards items: - enum: + - ply,plyaqm # Plymovent AQM board - prt,mecio1r0 # Protonic MECIO1r0 - prt,mect1s # Protonic MECT1S - prt,prtt1a # Protonic PRTT1A @@ -94,6 +101,8 @@ properties: - description: Octavo OSD32MP153 System-in-Package based boards items: - enum: + - lxa,stm32mp153c-fairytux2-gen1 # Linux Automation FairyTux 2 (Generation 1) + - lxa,stm32mp153c-fairytux2-gen2 # Linux Automation FairyTux 2 (Generation 2) - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3) - const: oct,stm32mp153x-osd32 - const: st,stm32mp153 @@ -178,9 +187,22 @@ properties: - description: ST STM32MP257 based Boards items: - enum: + - st,stm32mp257f-dk - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: ST STM32MP235 based Boards + items: + - enum: + - st,stm32mp235f-dk + - const: st,stm32mp235 + + - description: ST STM32MP215 based Boards + items: + - enum: + - st,stm32mp215f-dk + - const: st,stm32mp215 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 046536d02706..f536cdd2c1a6 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -589,6 +589,11 @@ properties: - const: emlid,neutis-n5h3 - const: allwinner,sun8i-h3 + - description: NetCube Systems Kumquat + items: + - const: netcube,kumquat + - const: allwinner,sun8i-v3s + - description: NextThing Co. CHIP items: - const: nextthing,chip diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documentation/devicetree/bindings/arm/ti/omap.yaml index 93e04a109a12..3603edd7361d 100644 --- a/Documentation/devicetree/bindings/arm/ti/omap.yaml +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -141,6 +141,13 @@ properties: - const: ti,omap4430 - const: ti,omap4 + - description: OMAP4 PandaBoard Revision A4 and later + items: + - const: ti,omap4-panda-a4 + - const: ti,omap4-panda + - const: ti,omap4430 + - const: ti,omap4 + - description: OMAP4 DuoVero with Parlor expansion board/daughter board items: - const: gumstix,omap4-duovero-parlor diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 9952e0ef7767..6ad78429dc74 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -163,11 +163,9 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/phy/phy.h> sata: ahci@fd0c0000 { @@ -175,7 +173,7 @@ examples: reg = <0xfd0c0000 0x200>; interrupt-parent = <&gic>; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zynqmp_clk SATA_REF>; + clocks = <&zynqmp_clk 22>; ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 000000000000..5a3ec902351c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi <ziyao@disroot.org> + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f13b..c15cc1752b02 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -31,6 +31,7 @@ properties: compatible: enum: - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top clocks: @@ -83,6 +84,24 @@ allOf: properties: compatible: contains: + const: samsung,exynos990-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: const: samsung,exynos990-cmu-top then: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index f448624dd779..193ddb105283 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - nvidia,tegra114-mipi + - nvidia,tegra124-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index ac3198953b8e..b5399c65a731 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -75,7 +75,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -84,7 +83,7 @@ examples: interrupts = <0 117 0x4>; #dma-cells = <1>; clock-names = "clk_main", "clk_apb"; - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; xlnx,bus-width = <128>; dma-coherent; }; diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml index 8cbad7e792b6..a403392fb263 100644 --- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -193,7 +193,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> bus { #address-cells = <2>; @@ -204,7 +203,7 @@ examples: interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; - clocks = <&zynqmp_clk AMS_REF>; + clocks = <&zynqmp_clk 70>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 4d67ff26d445..2836e4793afc 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -103,6 +103,7 @@ select: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos @@ -202,6 +203,7 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 3c30dd23cd4e..8d69846b2e09 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -197,7 +197,6 @@ examples: }; - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> @@ -210,9 +209,9 @@ examples: interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, + <&zynqmp_clk 51>, <&zynqmp_clk 50>, + <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 59a6af735a21..6e9a670eaf56 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -31,6 +31,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate - apple,t8103-pmgr-pwrstate - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 52e55077af1a..077b94f10dca 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - bananapi,bpi-f3 + - milkv,jupiter - const: spacemit,k1 additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index ebbf0c9109ce..e0f7503a9f35 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -22,7 +22,10 @@ description: | properties: compatible: - const: renesas,r9a09g057-sys + items: + - enum: + - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g057-sys # RZ/V2H reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 225c0f07ae94..51a4c48eea6d 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -493,6 +493,13 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - items: + - enum: + # MYIR Remi Pi SBC (MYB-YG2LX-REMI) + - myir,remi-pi + - const: renesas,r9a07g044l2 + - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) items: - enum: @@ -552,6 +559,15 @@ properties: - renesas,r9a09g057h41 # RZ/V2H - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support + - renesas,r9a09g057h45 # RZ/V2H with cryptographic extension support + - renesas,r9a09g057h46 # RZ/V2H with Mali-G31 + cryptographic extension support + - renesas,r9a09g057h48 # RZ/V2HP with Mali-G31 + Mali-C55 + cryptographic extension support + - const: renesas,r9a09g057 + + - description: Yuridenki-Shokai RZ/V2H Kakip + items: + - const: yuridenki,kakip + - const: renesas,r9a09g057h48 - const: renesas,r9a09g057 additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 61f38b68a4a3..2f61c1b95fea 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -15,6 +15,9 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3528-ioc-grf + - rockchip,rk3528-vo-grf + - rockchip,rk3528-vpu-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b046932fbc3..f711e23c0686 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -11,11 +11,21 @@ maintainers: - Krzysztof Kozlowski <krzk@kernel.org> description: | - USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). - USI shares almost all internal circuits within each protocol, so only one - protocol can be chosen at a time. USI is modeled as a node with zero or more - child nodes, each representing a serial sub-node device. The mode setting - selects which particular function will be used. + The USI IP-core provides configurable support for serial protocols, enabling + different serial communication modes depending on the version. + + In USIv1, configurations are available to enable either one or two protocols + simultaneously in select combinations - High-Speed I2C0, High-Speed + I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed + I2C1 and UART. + + In USIv2, only one protocol can be active at a time, either UART, SPI, or + High-Speed I2C. + + The USI core shares internal circuits across protocols, meaning only the + selected configuration is active at any given time. USI is modeled as a node + with zero or more child nodes, each representing a serial sub-node device. The + mode setting selects which particular function will be used. properties: $nodename: @@ -31,6 +41,7 @@ properties: - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi + - samsung,exynos8895-usi reg: maxItems: 1 @@ -64,7 +75,7 @@ properties: samsung,mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] + enum: [0, 1, 2, 3, 4, 5, 6] description: Selects USI function (which serial protocol to use). Refer to <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. @@ -101,37 +112,59 @@ required: - samsung,sysreg - samsung,mode -if: - properties: - compatible: - contains: - enum: - - samsung,exynos850-usi +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + + then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol + + clock-names: + maxItems: 2 + + samsung,mode: + enum: [0, 1, 2, 3] + + required: + - reg + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos8895-usi -then: - properties: - reg: - maxItems: 1 + then: + properties: + reg: false - clocks: - items: - - description: Bus (APB) clock - - description: Operating clock for UART/SPI/I2C protocol + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI protocol - clock-names: - maxItems: 2 + clock-names: + maxItems: 2 - required: - - reg - - clocks - - clock-names + samsung,clkreq-on: false -else: - properties: - reg: false - clocks: false - clock-names: false - samsung,clkreq-on: false + required: + - clocks + - clock-names additionalProperties: false @@ -144,7 +177,7 @@ examples: compatible = "samsung,exynos850-usi"; reg = <0x138200c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1010>; - samsung,mode = <USI_V2_UART>; + samsung,mode = <USI_MODE_UART>; samsung,clkreq-on; /* needed for UART mode */ #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index 131aba5ed9f4..fb5c39c79d28 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms maintainers: - Michal Simek <michal.simek@amd.com> -description: | - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC +description: + AMD/Xilinx boards with ARM 32/64bits cores properties: $nodename: @@ -187,6 +187,13 @@ properties: - const: qemu,mbv - const: amd,mbv + - description: Xilinx Versal NET VN-X revA platform + items: + enum: + - xlnx,versal-net-vnx-revA + - xlnx,versal-net-vnx + - xlnx,versal-net + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/sound/ics43432.txt b/Documentation/devicetree/bindings/sound/ics43432.txt deleted file mode 100644 index e6f05f2f6c4e..000000000000 --- a/Documentation/devicetree/bindings/sound/ics43432.txt +++ /dev/null @@ -1,19 +0,0 @@ -Invensense ICS-43432-compatible MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the only -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible: should be one of the following. - "invensense,ics43432": For the Invensense ICS43432 - "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR - -Example: - - ics43432: ics43432 { - compatible = "invensense,ics43432"; - }; diff --git a/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml new file mode 100644 index 000000000000..7bd984817aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/invensense,ics43432.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Invensense ICS-43432-compatible MEMS Microphone with I2S Output + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + +description: + The ICS-43432 and compatible MEMS microphones output audio over an I2S + interface and require no software configuration. The only host connection + is the I2S bus. The microphone requires an I2S clock frequency between + 460 kHz and 3.379 MHz and 64 clock cycles per stereo frame. Each frame + contains 32-bit slots per channel, with 24 bits carrying audio data. + A hardware pin determines whether the microphone outputs audio on the + left or right channel of the I2S frame. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - invensense,ics43432 + - cui,cmm-4030d-261 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ics43432: ics43432 { + compatible = "invensense,ics43432"; + + port { + endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml index 12c31b4b99e1..3ca9affb79a2 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml @@ -28,6 +28,7 @@ properties: - nvidia,tegra186-hda - nvidia,tegra210-hda - nvidia,tegra124-hda + - nvidia,tegra114-hda - const: nvidia,tegra30-hda - items: - const: nvidia,tegra132-hda diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 04d4d3b4916d..02cf1314367b 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -65,14 +65,13 @@ allOf: examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> soc { #address-cells = <2>; #size-cells = <2>; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; - clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 00f87a558c7d..b5843f4d17d8 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -101,7 +101,6 @@ examples: #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> axi { @@ -113,7 +112,7 @@ examples: #size-cells = <0x2>; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index ef3143f4b794..004d3ebec091 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -106,6 +106,10 @@ properties: - description: USB3/SS(P) PHY - description: USB2/HS PHY + port: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) Output endpoint to a Type-C connector + vusb33-supply: description: Regulator of USB AVDD3.3v diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index d4e187c78a0b..21fc6bbe954f 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -155,6 +155,18 @@ properties: property is used. See graph.txt $ref: /schemas/graph.yaml#/properties/port + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: High Speed (HS) data bus. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) data bus. + enable-manual-drd: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b5979832ddce..0ef0bc6449ec 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -147,6 +147,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^ariaboard,.*": + description: Shanghai Novotech Co., Ltd. (Ariaboard) "^aries,.*": description: Aries Embedded GmbH "^arm,.*": @@ -1033,6 +1035,8 @@ patternProperties: description: Neofidelity Inc. "^neonode,.*": description: Neonode Inc. + "^netcube,.*": + description: NetCube Systems Austria "^netgear,.*": description: NETGEAR "^netlogic,.*": @@ -1204,6 +1208,8 @@ patternProperties: description: Primux Trading, S.L. "^probox2,.*": description: PROBOX2 (by W2COMP Co., Ltd.) + "^pri,.*": + description: Priva "^prt,.*": description: Protonic Holland "^pulsedlight,.*": @@ -1269,7 +1275,7 @@ patternProperties: "^riscv,.*": description: RISC-V Foundation "^rockchip,.*": - description: Fuzhou Rockchip Electronics Co., Ltd + description: Rockchip Electronics Co., Ltd. "^rocktech,.*": description: ROCKTECH DISPLAYS LIMITED "^rohm,.*": @@ -1739,6 +1745,8 @@ patternProperties: description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": description: Y Soft Corporation a.s. + "^yuridenki,.*": + description: Yuridenki-Shokai Co. Ltd. "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": diff --git a/MAINTAINERS b/MAINTAINERS index 1cd25139cc58..0025e87585ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2757,6 +2757,13 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut +ARM/MORELLO PLATFORM +M: Vincenzo Frascino <vincenzo.frascino@arm.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/arm,morello.yaml +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski <krzk@kernel.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -20528,7 +20535,10 @@ F: drivers/perf/riscv_pmu_sbi.c RISC-V SPACEMIT SoC Support M: Yixun Lan <dlan@gentoo.org> L: linux-riscv@lists.infradead.org +L: spacemit@lists.linux.dev S: Maintained +W: https://github.com/spacemit-com/linux/wiki +C: irc://irc.libera.chat/spacemit T: git https://github.com/spacemit-com/linux F: arch/riscv/boot/dts/spacemit/ N: spacemit @@ -22285,7 +22295,9 @@ F: include/linux/sony-laptop.h SOPHGO DEVICETREES and DRIVERS M: Chen Wang <unicorn_wang@outlook.com> -M: Inochi Amaoto <inochiama@outlook.com> +M: Inochi Amaoto <inochiama@gmail.com> +L: sophgo@lists.linux.dev +W: https://github.com/sophgo/linux/wiki T: git https://github.com/sophgo/linux.git S: Maintained N: sophgo diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 48666f73e638..d799ad153b37 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -199,6 +199,7 @@ DTC_FLAGS_sun8i-h3-nanopi-r1 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ +DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ sun8i-a23-gt90h-v4.dtb \ @@ -261,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v3s-netcube-kumquat.dtb \ sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts new file mode 100644 index 000000000000..5143cb4e7b78 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li> + */ + +/dts-v1/; +#include "sun8i-v3s.dtsi" + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> + +/{ + model = "NetCube Systems Kumquat"; + compatible = "netcube,kumquat", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + rtc0 = &ds3232; + rtc1 = &rtc; /* not battery backed */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 40 MHz Crystal Oscillator on PCB */ + clk_can0: clock-can0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-user { + label = "GPIO Key User"; + linux,code = <KEY_PROG1>; + gpios = <&pio 1 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PB2 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-heartbeat { + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + }; + + led-mmc0-act { + gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + linux,default-trigger = "mmc0"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + }; + }; + + /* EA3036C Switching 3 Channel Regulator - Channel 2 */ + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + }; + + /* K7805-1000R3 Switching Regulator supplied from main 12/24V terminal block */ + reg_vcc5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "MIC1", "Mic", + "Mic", "HBIAS"; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&emac { + allwinner,leds-active-low; + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@fa { + reg = <0xfa 0x06>; + }; + }; + + tusb320: typec@60 { + compatible = "ti,tusb320"; + reg = <0x60>; + interrupts-extended = <&pio 1 5 IRQ_TYPE_LEVEL_LOW>; /* PB5 */ + }; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +/* Exposed as the Flash/SD Header on the board */ +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&osc32k { + status = "disabled"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "CAN_nCS", "CAN_nINT", "USER_SW", "PB3", // PB + "USB_ID", "USBC_nINT", "I2C0_SCL", "I2C0_SDA", + "UART0_TX", "UART0_RX", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SPI_MISO", "SPI_SCK", "FLASH_nCS", "SPI_MOSI", // PC + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "Q12", "Q11", "Q10", "Q9", // PE + "LED_SYS0", "I1", "Q1", "Q2", + "I2", "I3", "Q3", "Q4", + "I4", "I5", "Q5", "Q6", + "I6", "I7", "Q7", "Q8", + "I8", "UART1_TXD", "UART1_RXD", "ESP_nRST", + "ESP_nBOOT", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CMD", // PF + "SD_D3", "SD_D2", "LED_SYS1", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&rtc { + /delete-property/ clocks; +}; + +/* Exposed as a USB-C connector with USB-Serial converter */ +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 = <&uart1_pe_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + extcon = <&tusb320 0>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + status = "okay"; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <0>, <&pio 1 0 GPIO_ACTIVE_LOW>; /* PB0 */ + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + label = "firmware"; + spi-max-frequency = <40000000>; + }; + + can@1 { + compatible = "microchip,mcp2518fd"; + reg = <1>; + clocks = <&clk_can0>; + interrupts-extended = <&pio 1 1 IRQ_TYPE_LEVEL_LOW>; /* PB1 */ + spi-max-frequency = <20000000>; + vdd-supply = <®_vcc3v3>; + xceiver-supply = <®_vcc3v3>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index 9e13c2aa8911..f909b1d4dbca 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -416,6 +416,12 @@ function = "uart0"; }; + /omit-if-no-ref/ + uart1_pe_pins: uart1-pe-pins { + pins = "PE21", "PE22"; + function = "uart1"; + }; + uart2_pins: uart2-pins { pins = "PB0", "PB1"; function = "uart2"; diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 9ff142d9fe3f..847f7b1f1e96 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -449,7 +449,11 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -699,11 +703,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts index 18ea6592b7d7..236999548094 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts @@ -443,8 +443,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts index fb28cb330f17..0bca0b33eea2 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts @@ -162,8 +162,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &uart_AO { diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts index 2aa012f38a3b..1cd2093202ca 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -347,8 +347,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 9e02a97f86a0..0876611ce26a 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -403,8 +403,12 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; @@ -674,11 +678,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts index 808cd5778e27..adc74243ed19 100644 --- a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -88,7 +88,7 @@ }; &portd { - lcden { + lcden-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts index 19d56e9aec9d..a351a97d257e 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -8,6 +8,7 @@ #include "intel-ixp42x.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "Netgear WG302 v1"; @@ -32,6 +33,35 @@ serial0 = &uart1; }; + leds { + compatible = "gpio-leds"; + test_led: led-test { + color = <LED_COLOR_ID_AMBER>; + function = "test"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wlan_led: led-wlan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "phy0tx"; + }; + }; + + gpio_keys { + /* RESET is on GPIO13 which can't fire interrupts */ + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-reset { + linux,code = <KEY_RESTART>; + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + soc { bus@c4000000 { flash@0,0 { @@ -57,7 +87,7 @@ status = "okay"; /* - * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) + * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) * We have slots (IDSEL) 1 and 2 with one assigned IRQ * each handling all IRQs. */ @@ -70,10 +100,10 @@ <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ - <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ }; ethernet@c8009000 { diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi index 51a716c59669..0adeccabd4fe 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -193,10 +193,10 @@ compatible = "intel,ixp4xx-ethernet"; reg = <0xc800c000 0x1000>; status = "disabled"; - intel,npe = <0>; /* Dummy values that depend on firmware */ queue-rx = <&qmgr 0>; queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 0>; }; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 8208c6a9627a..7aa71a9aa1bb 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -453,7 +453,7 @@ pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; - wifi-disable { + wifi-disable-hog { gpio-hog; gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; output-low; @@ -465,7 +465,7 @@ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; - lte-disable { + lte-disable-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-low; @@ -476,14 +476,14 @@ * This signal, when asserted, isolates Armada 38x sample at reset pins * from control of external devices. Should be de-asserted after reset. */ - sar-isolation { + sar-isolation-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_LOW>; output-low; line-name = "sar-isolation"; }; - poe-reset { + poe-reset-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts index f7daa3bc707e..cf32ba9b4e8e 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts @@ -34,7 +34,7 @@ }; &gpio0 { - phy1_reset { + phy1-reset-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi index 47f03c69c55a..9d7cff4feada 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi @@ -53,7 +53,7 @@ cd-gpios = <&gpio0 29 9>; }; gpio@10100 { - p28 { + p28-hog { gpio-hog; gpios = <28 GPIO_ACTIVE_HIGH>; /* @@ -71,7 +71,7 @@ }; }; gpio@10140 { - p2 { + p2-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; /* diff --git a/arch/arm/boot/dts/microchip/aks-cdu.dts b/arch/arm/boot/dts/microchip/aks-cdu.dts index b65f80e1ef05..302cb872efa1 100644 --- a/arch/arm/boot/dts/microchip/aks-cdu.dts +++ b/arch/arm/boot/dts/microchip/aks-cdu.dts @@ -56,7 +56,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/animeo_ip.dts b/arch/arm/boot/dts/microchip/animeo_ip.dts index 7f527622d3f2..c11f4f7dac94 100644 --- a/arch/arm/boot/dts/microchip/animeo_ip.dts +++ b/arch/arm/boot/dts/microchip/animeo_ip.dts @@ -136,7 +136,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/microchip/at91-foxg20.dts b/arch/arm/boot/dts/microchip/at91-foxg20.dts index 9dfd5de808d1..8e9e87665045 100644 --- a/arch/arm/boot/dts/microchip/at91-foxg20.dts +++ b/arch/arm/boot/dts/microchip/at91-foxg20.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-qil_a9260.dts b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts index 5ccb3c139592..892dbd8dbbed 100644 --- a/arch/arm/boot/dts/microchip/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts @@ -114,7 +114,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts index 2fb51b9aca2a..49dc1a4ccb36 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts @@ -105,7 +105,7 @@ status = "okay"; }; - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts index f3ffb8f01d8a..45edf6214cf7 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts @@ -37,7 +37,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ &pioA PIN_PA27 GPIO_ACTIVE_HIGH @@ -48,7 +48,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts index e4ae60ef5f8a..10d69f6957cf 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts @@ -47,7 +47,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioA PIN_PB12 GPIO_ACTIVE_HIGH @@ -58,7 +58,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts index 4bab3f25b855..7e77a55ed41d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts @@ -46,7 +46,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ &pioA PIN_PB10 GPIO_ACTIVE_HIGH @@ -57,7 +57,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts index 5662992cf213..d2c43957497d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts @@ -283,7 +283,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 3 GPIO_ACTIVE_LOW @@ -294,7 +294,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts index 8adf567f2f0f..b9725e400501 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts @@ -22,7 +22,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -31,7 +31,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts index 95d701d13fef..0ecccb9a809d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts @@ -164,7 +164,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_HIGH @@ -175,7 +175,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts index 20ac775059ca..69107d6cd26c 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts @@ -198,7 +198,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ &pioE 11 GPIO_ACTIVE_LOW @@ -207,7 +207,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 0f86360fb733..30fdc4f55a3b 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -32,6 +32,18 @@ }; }; +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + &flx6 { atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; status = "okay"; @@ -43,11 +55,63 @@ status = "okay"; }; +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; +}; + +&i2c10 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "okay"; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <47000>; + label = "VDD3V3"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDIODDR"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCORE"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCPU"; + }; + }; +}; + &main_xtal { clock-frequency = <24000000>; }; &pioa { + pinctrl_i2c10_default: i2c10-default{ + pinmux = <PIN_PB19__FLEXCOM10_IO1>, + <PIN_PB20__FLEXCOM10_IO0>; + bias-pull-up; + }; + pinctrl_sdmmc1_default: sdmmc1-default { cmd-data { pinmux = <PIN_PB22__SDMMC1_CMD>, @@ -84,6 +148,15 @@ status = "okay"; }; +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts index 0f5e6ad438dd..2543599013b1 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -137,6 +137,7 @@ vref-supply = <&vddout25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts index ecbdacf48708..c5fc51667066 100644 --- a/arch/arm/boot/dts/microchip/at91-vinco.dts +++ b/arch/arm/boot/dts/microchip/at91-vinco.dts @@ -162,7 +162,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -171,7 +171,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { /* 4G Modem */ status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi index 02a838541dc3..2a4c83d88733 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -702,7 +702,7 @@ status = "disabled"; }; - usb0: ohci@300000 { + usb0: usb@300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts index 0bf472b157a5..ce691c4692b9 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200ek.dts +++ b/arch/arm/boot/dts/microchip/at91rm9200ek.dts @@ -89,7 +89,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi index 0038183e9a53..ec973f07a961 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -742,7 +742,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9260ek.dts b/arch/arm/boot/dts/microchip/at91sam9260ek.dts index e8e65e60564d..8522a210b484 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9260ek.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi index b57a7fd67197..0b556c234557 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -77,7 +77,7 @@ #size-cells = <1>; ranges; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9261ek.dts b/arch/arm/boot/dts/microchip/at91sam9261ek.dts index a8f523131cd6..313bc2797fde 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9261ek.dts @@ -31,7 +31,7 @@ }; ahb { - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi index b95d4016ae9f..3e9e5ce7c6c8 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi @@ -768,7 +768,7 @@ status = "disabled"; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts index f25692543d71..471ea25296aa 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9263ek.dts @@ -207,7 +207,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi index 4e7cfbbd4241..84a7287107f8 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi @@ -211,7 +211,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi index 157d306ef5c9..535e26e05e99 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -964,7 +964,7 @@ status = "disabled"; }; - usb0: ohci@700000 { + usb0: usb@700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -973,7 +973,7 @@ status = "disabled"; }; - usb1: ehci@800000 { + usb1: usb@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts index 071db4f16313..2a31b2f14893 100644 --- a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts @@ -303,14 +303,14 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW &pioD 3 GPIO_ACTIVE_LOW>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi index 844bd50943fc..2f930c39ce4d 100644 --- a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi @@ -748,7 +748,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12ek.dts b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts index 643c3b2ab97e..b06a54e8e237 100644 --- a/arch/arm/boot/dts/microchip/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts @@ -180,7 +180,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <1>; atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi index 27c1f2861cc3..17bdf1e4db01 100644 --- a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -886,7 +886,7 @@ }; }; - usb0: ohci@600000 { + usb0: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -895,7 +895,7 @@ status = "disabled"; }; - usb1: ehci@700000 { + usb1: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/ethernut5.dts b/arch/arm/boot/dts/microchip/ethernut5.dts index ad7a0850252a..52ccef31b391 100644 --- a/arch/arm/boot/dts/microchip/ethernut5.dts +++ b/arch/arm/boot/dts/microchip/ethernut5.dts @@ -101,7 +101,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/evk-pro3.dts b/arch/arm/boot/dts/microchip/evk-pro3.dts index 6d519d02d190..40c5111c2f0a 100644 --- a/arch/arm/boot/dts/microchip/evk-pro3.dts +++ b/arch/arm/boot/dts/microchip/evk-pro3.dts @@ -45,7 +45,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/mpa1600.dts b/arch/arm/boot/dts/microchip/mpa1600.dts index 005c2758e229..2a97e2c0b894 100644 --- a/arch/arm/boot/dts/microchip/mpa1600.dts +++ b/arch/arm/boot/dts/microchip/mpa1600.dts @@ -57,7 +57,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/pm9g45.dts b/arch/arm/boot/dts/microchip/pm9g45.dts index c349fd3758a6..2258e62f5864 100644 --- a/arch/arm/boot/dts/microchip/pm9g45.dts +++ b/arch/arm/boot/dts/microchip/pm9g45.dts @@ -139,12 +139,12 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index b8b2c1ddf3f1..b075865e6a76 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -88,7 +88,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -97,7 +97,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi index 3f99451aef83..dc22fb679333 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -136,7 +136,7 @@ status = "disabled"; }; - usb1: ohci@400000 { + usb1: usb@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -145,7 +145,7 @@ status = "disabled"; }; - usb2: ehci@500000 { + usb2: usb@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi index 70f380c399ce..e95799c17fdb 100644 --- a/arch/arm/boot/dts/microchip/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -1074,7 +1074,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1083,7 +1083,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi index 3652c9e24124..90da04b84b39 100644 --- a/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi @@ -172,7 +172,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH &pioD 26 GPIO_ACTIVE_LOW @@ -181,7 +181,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi index 355132628604..59a7d557c7cb 100644 --- a/arch/arm/boot/dts/microchip/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -119,7 +119,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -128,7 +128,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 854b30d15dcd..b6710ccd4c36 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -9,6 +9,7 @@ */ #include <dt-bindings/clock/at91.h> +#include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -52,6 +53,11 @@ #address-cells = <1>; #size-cells = <1>; + sfrbu: sfr@e0008000 { + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -76,6 +82,31 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + ps_wdt: watchdog@e001d000 { + compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; + reg = <0xe001d000 0x30>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 0>; + }; + + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d200 0x20>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -83,6 +114,29 @@ #clock-cells = <1>; }; + rtc: rtc@e001d800 { + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d800 0x30>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 1>; + }; + + chipid@e0020000 { + compatible = "microchip,sama7d65-chipid"; + reg = <0xe0020000 0x8>; + }; + + dma2: dma-controller@e1200000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1200000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "dma_clk"; + dma-requests = <0>; + status = "disabled"; + }; + sdmmc1: mmc@e1208000 { compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1208000 0x400>; @@ -95,6 +149,26 @@ status = "disabled"; }; + dma0: dma-controller@e1610000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1610000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + dma1: dma-controller@e1614000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1614000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "dma_clk"; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x100>; @@ -132,6 +206,27 @@ }; }; + flx10: flexcom@e2824000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2824000 0x200>; + ranges = <0x0 0xe2824000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, diff --git a/arch/arm/boot/dts/microchip/tny_a9260.dts b/arch/arm/boot/dts/microchip/tny_a9260.dts index ef6d586ce887..f0f2a787d669 100644 --- a/arch/arm/boot/dts/microchip/tny_a9260.dts +++ b/arch/arm/boot/dts/microchip/tny_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board + * tny_a9260.dts - Device Tree file for Calao TNY A9260 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi index 70e5635c78ed..4d4377f51bec 100644 --- a/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board + * tny_a9260_common.dtsi - Device Tree file for Calao TNY A926x board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts index 62b7d9f9a926..3dd48b3e06da 100644 --- a/arch/arm/boot/dts/microchip/tny_a9263.dts +++ b/arch/arm/boot/dts/microchip/tny_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/tny_a9g20.dts b/arch/arm/boot/dts/microchip/tny_a9g20.dts index 118d766a1265..cebd5696a2c1 100644 --- a/arch/arm/boot/dts/microchip/tny_a9g20.dts +++ b/arch/arm/boot/dts/microchip/tny_a9g20.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board + * tny_a9g20.dts - Device Tree file for Calao TNY A9G20 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts index 66f8da89007d..e7f7b259ccf3 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board + * usb_a9260.dts - Device Tree file for Calao USB A9260 board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi index 8744b5f6f792..8c3530638c6d 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board + * usb_a926x.dts - Device Tree file for Calao USB A926x board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -111,7 +111,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; @@ -122,17 +122,14 @@ user_led { label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/microchip/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts index 45745915b2e1..60d7936dc562 100644 --- a/arch/arm/boot/dts/microchip/usb_a9263.dts +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -9,7 +9,7 @@ / { model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + compatible = "calao,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; chosen { bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; @@ -139,7 +139,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; }; @@ -151,16 +151,13 @@ user_led { label = "user_led"; gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi index 08d58081201a..5b1d80c0ab26 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi @@ -65,28 +65,26 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb1 { + button-user-pb1 { label = "user_pb1"; gpios = <&pioB 25 GPIO_ACTIVE_LOW>; linux,code = <0x100>; }; - user_pb2 { + button-user-pb2 { label = "user_pb2"; gpios = <&pioB 13 GPIO_ACTIVE_LOW>; linux,code = <0x101>; }; - user_pb3 { + button-user-pb3 { label = "user_pb3"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <0x102>; }; - user_pb4 { + button-user-pb4 { label = "user_pb4"; gpios = <&pioC 9 GPIO_ACTIVE_LOW>; linux,code = <0x103>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts index 2f667b083e81..a2f748141d4b 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board * * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi index 7d10b36db1ee..f1946e0996b7 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board * * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts index f65712015d40..4d104797176c 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board + * usb_a9g20_lpw.dts - Device Tree file for Calao USB A9G20 Low Power board * * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -16,7 +16,7 @@ spi1: spi@fffcc000 { cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; status = "okay"; - mmc-slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3200 3400>; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 86f14e2fd29f..4caf2073c556 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -139,7 +139,7 @@ reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 82>; reset-names = "dsi"; @@ -577,6 +577,21 @@ #iommu-cells = <1>; }; + hda@70030000 { + compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HDA>, + <&tegra_car TEGRA114_CLK_HDA2HDMI>, + <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + ahub@70080000 { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>, @@ -805,31 +820,40 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index 8f1fff373461..ec4f0e346b2b 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -165,6 +165,22 @@ status = "disabled"; }; + dsia: dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54300000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + vic@54340000 { compatible = "nvidia,tegra124-vic"; reg = <0x0 0x54340000 0x0 0x00040000>; @@ -177,6 +193,22 @@ iommus = <&mc TEGRA_SWGROUP_VIC>; }; + dsib: dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54400000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; @@ -938,6 +970,14 @@ }; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x0 0x700e3000 0x0 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + clock-names = "mipi-cal"; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0 0x70110000 0 0x100>, /* DFLL control */ diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index e118809dc6d9..67764afeb013 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -1085,6 +1085,17 @@ sbs,poll-retry-count = <10>; power-supplies = <&mains>; }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3000a"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&vdd_1v8_sys>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 39a153536d2a..8b3abe817e12 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -69,6 +69,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-colibri-iris.dtb \ imx6dl-colibri-iris-v2.dtb \ + imx6dl-colibri-v1.2-aster.dtb \ + imx6dl-colibri-v1.2-eval-v3.dtb \ + imx6dl-colibri-v1.2-iris.dtb \ + imx6dl-colibri-v1.2-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ @@ -158,6 +162,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ imx6q-apalis-ixora-v1.2.dtb \ + imx6q-apalis-v1.2-eval.dtb \ + imx6q-apalis-v1.2-eval-v1.2.dtb \ + imx6q-apalis-v1.2-ixora.dtb \ + imx6q-apalis-v1.2-ixora-v1.1.dtb \ + imx6q-apalis-v1.2-ixora-v1.2.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ imx6q-b450v3.dtb \ @@ -329,6 +338,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ + imx6ul-var-som-concerto.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi index 00006c90d9a7..813a81558c40 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -340,7 +340,7 @@ #address-cells = <1>; #size-cells = <1>; - nfc: nand@b8000000 { + nfc: nand-controller@b8000000 { compatible = "fsl,imx31-nand", "fsl,imx27-nand"; reg = <0xb8000000 0x1000>; interrupts = <33>; diff --git a/arch/arm/boot/dts/nxp/imx/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi index 1b6f444443dd..d76c496b3f71 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx50.dtsi @@ -338,7 +338,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx50-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi index cc88da4d7785..8323e3a56a1f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -458,7 +458,7 @@ clks: ccm@73fd4000 { compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts index c14eb7280f09..3cdb87ac1d7c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts @@ -162,7 +162,7 @@ }; expander: pca9554@20 { - compatible = "pca9554"; + compatible = "nxp,pca9554"; reg = <0x20>; interrupts = <109>; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index e939acc1c88b..2892e457fea7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -593,7 +593,7 @@ touchscreen@4b { compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; reg = <0x4b>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi index 845e2bf8460a..faac7cc249d0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53.dtsi @@ -598,7 +598,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx53-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts new file mode 100644 index 000000000000..44c78c07f431 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-aster.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Aster Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts new file mode 100644 index 000000000000..93fd0af53a3c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Evaluation Board V3"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts new file mode 100644 index 000000000000..92d41fc9a13f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris-v2.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris V2 Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts new file mode 100644 index 000000000000..c8957948c887 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts new file mode 100644 index 000000000000..908dab57fd87 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board v1.2"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts new file mode 100644 index 000000000000..5463d4127382 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts new file mode 100644 index 000000000000..84eabf81ba84 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.1.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.1"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts new file mode 100644 index 000000000000..d7cfab4de457 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.2"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts new file mode 100644 index 000000000000..189b074e31ce --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi new file mode 100644 index 000000000000..83fa04fc9f18 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Apalis AN1_ADC0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_TSWIP_ADC3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi index 88be29166c1a..b13000a62a7b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -664,7 +663,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi new file mode 100644 index 000000000000..d11bf911b728 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Colibri AIN0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 9f33419c260b..3525cbcda57f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Colibri iMX6DL/S Module"; - compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -588,7 +587,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 8cefda70db63..ee2c6bec92e8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -124,7 +124,7 @@ compatible = "fsl,imx-audio-tlv320aic32x4"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&ssi1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi index 6152a9ed4768..07492f63a1f8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi @@ -7,16 +7,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -/ { - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -25,11 +15,16 @@ m25p80: flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; + spi-max-frequency = <50000000>; + vcc-supply = <&sw4_reg>; m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; @@ -119,7 +114,7 @@ }; sw4_reg: sw4 { - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -183,7 +178,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&sw4_reg>; non-removable; disable-wp; no-sd; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi index 828996382f24..e8fd37dd8835 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -30,14 +30,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi index 1d0966b8d99e..0e404c1f62f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -23,14 +23,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 0e839bbfea08..911ccbd132cf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -62,6 +62,33 @@ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -139,6 +166,11 @@ wlf,gpio-cfg = <1 3>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; camera@3c { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index c9c0794f01a2..2dd635a615cb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -162,13 +162,18 @@ status = "okay"; flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; + reg = <0>; spi-max-frequency = <33000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; - reg = <0>; + vcc-supply = <®_vldo4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts index f2a5f17f312e..2e7b96e7b791 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts @@ -6,8 +6,9 @@ /dts-v1/; -#include "imx6ul-tqma6ul1.dtsi" +#include "imx6ul-tqma6ul2.dtsi" #include "mba6ulx.dtsi" +#include "imx6ul-tqma6ul1.dtsi" / { model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi index 24192d012ef7..79c8c5529135 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi @@ -4,8 +4,6 @@ * Author: Markus Niebel <Markus.Niebel@tq-group.com> */ -#include "imx6ul-tqma6ul2.dtsi" - / { model = "TQ-Systems TQMa6UL1 SoM"; compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts new file mode 100644 index 000000000000..9ff3b374a2b3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Variscite SoM mounted on it + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include "imx6ul-var-som.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Variscite VAR-SOM-MX6UL Concerto Board"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; + + key-back { + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + }; + + key-wakeup { + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "gpled2"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + /* + * To actually use this interrupt + * connect pins J14.8 & J14.10 on the Concerto-Board. + */ + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_gpio_key_back: gpio-key-backgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 + >; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&tsc { + /* + * Conflics with wdog1 ext-reset-output & SD CD pins, + * so we keep it disabled by default. + */ + status = "disabled"; +}; + +/* Console UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* ttymxc4 UART */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + /* + * To actually use ext-reset-output + * connect pins J17.3 & J17.8 on the Concerto-Board + */ + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi new file mode 100644 index 000000000000..4e536e0252de --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-MX6UL Module + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +/dts-v1/; + +#include "imx6ul.dtsi" +#include <dt-bindings/clock/imx6ul-clock.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Variscite VAR-SOM-MX6UL module"; + compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_gpio_dvfs: reg-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + dc-supply = <®_gpio_dvfs>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; + +&pxp { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi index 576a7df505d3..4d948a9757f9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -170,7 +170,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-routing = diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index aa8f65cd4adf..2966a33bc528 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -265,6 +265,13 @@ spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; + vcc-supply = <&vgen4_reg>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index 6cde84636900..17236f90ab33 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -143,6 +143,33 @@ gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; @@ -406,6 +433,11 @@ <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 22dd72499ef2..2629968001a7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -176,6 +176,34 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -529,34 +557,6 @@ #mux-control-cells = <1>; mux-reg-masks = <0x14 0x00000010>; }; - - video_mux: csi-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - csi_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_csi_mux>; - }; - }; - - port@2 { - reg = <2>; - - csi_mux_to_csi: endpoint { - remote-endpoint = <&csi_from_csi_mux>; - }; - }; - }; }; ocotp: efuse@30350000 { diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index 941d9860218e..67a3d484bc9f 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -142,7 +142,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile index a430d04f9c69..96dd31ea19ba 100644 --- a/arch/arm/boot/dts/nxp/mxs/Makefile +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -8,6 +8,9 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-apf28.dtb \ imx28-apf28dev.dtb \ imx28-apx4devkit.dtb \ + imx28-btt3-0.dtb \ + imx28-btt3-1.dtb \ + imx28-btt3-2.dtb \ imx28-cfa10036.dtb \ imx28-cfa10037.dtb \ imx28-cfa10049.dtb \ diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts new file mode 100644 index 000000000000..6ac46e4b21bb --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +&hog_pins_rev { + fsl,pull-up = <MXS_PULL_ENABLE>; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts new file mode 100644 index 000000000000..213fe931c58b --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts new file mode 100644 index 000000000000..4bccd784d065 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +/ { + panel { + compatible = "powertip,st7272", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <68>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi new file mode 100644 index 000000000000..2c52e67e5c14 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + model = "BTT3"; + + compatible = "lwn,imx28-btt3", "fsl,imx28"; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1 quiet"; + }; + + memory@40000000 { + reg = <0x40000000 0x10000000>; + device_type = "memory"; + }; + + panel { + compatible = "powertip,hx8238a", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <38>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "BTTC Audio"; + simple-audio-card,widgets = "Speaker", "BTTC Speaker"; + simple-audio-card,routing = "BTTC Speaker", "SPKOUTN", "BTTC Speaker", "SPKOUTP"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + bitclock-master = <&dai0_master>; + frame-master = <&dai0_master>; + mclk-fs = <256>; + + dai0_master: cpu { + sound-dai = <&saif0>; + }; + + codec { + sound-dai = <&wm89xx>; + clocks = <&saif0>; + }; + }; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pin_bttc>; + reset-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + /* W1-163 needs 60us for WL_EN to be low and */ + /* 150ms after high before downloading FW is possible */ + post-power-on-delay-ms = <200>; + power-off-delay-us = <100>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + wm89xx: audio-codec@1a { + compatible = "wlf,wm8940"; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>, <&lcdif_sync_pins_bttc>, + <&lcdif_reset_pins_bttc>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&mac0 { + clocks = <&clks 57>, <&clks 57>, <&clks 64>; + clock-names = "ipg", "ahb", "enet_out"; + phy-handle = <&mac0_phy>; + phy-mode = "rmii"; + phy-supply = <®_3v3>; + /* + * This MAC address is adjusted during production. + * Value specified below is used as a fallback during recovery. + */ + local-mac-address = [ 00 11 B8 00 BF 8A ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mac0_phy: ethernet-phy@0 { + /* LAN8720Ai - PHY ID */ + compatible = "ethernet-phy-id0007.c0f0","ethernet-phy-ieee802.3-c22"; + reg = <0>; + smsc,disable-energy-detect; + max-speed = <100>; + reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>, <&hog_pins_rev>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_GPMI_WRN__GPIO_0_25 + MX28_PAD_ENET0_RXD2__GPIO_4_9 + MX28_PAD_ENET0_TXD2__GPIO_4_11 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_rev: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RXD3__GPIO_4_10 + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 + MX28_PAD_ENET0_COL__GPIO_4_14 + MX28_PAD_ENET0_CRS__GPIO_4_15 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + keypad_pins_bttc: keypad-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_AUART0_CTS__GPIO_3_2 + MX28_PAD_AUART0_RTS__GPIO_3_3 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_CE2N__GPIO_0_18 + MX28_PAD_GPMI_CE3N__GPIO_0_19 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_sync_pins_bttc: lcdif-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_RD_E__LCD_VSYNC + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_reset_pins_bttc: lcdif-bttc@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + ssp1_sdio_pins_a: ssp1-sdio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP1_DATA0__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_SSP1_DATA3__SSP1_D3 + MX28_PAD_SSP1_CMD__SSP1_CMD + MX28_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + wifi_en_pin_bttc: wifi-en-pin@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CLE__GPIO_0_27 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; +}; + +®_usb_5v { + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + #sound-dai-cells = <0>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_sdio_pins_a>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + vmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + status = "okay"; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts index 0f01dded4e3d..ca62e7933116 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts @@ -24,30 +24,25 @@ }; leds { - #address-cells = <1>; - #size-cells = <0>; compatible = "gpio-leds"; status = "okay"; - led@1 { + led-1 { label = "sps1-1:yellow:user"; gpios = <&gpio0 6 0>; linux,default-trigger = "heartbeat"; - reg = <0>; }; - led@2 { + led-2 { label = "sps1-2:red:user"; gpios = <&gpio0 3 0>; linux,default-trigger = "heartbeat"; - reg = <1>; }; - led@3 { + led-3 { label = "sps1-3:red:user"; gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; + linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts index 722182f5fd17..2492fb99956c 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts @@ -119,7 +119,7 @@ status = "okay"; spidev0@0 { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; reg = <0>; fsl,spi-cs-sck-delay = <200>; @@ -136,7 +136,7 @@ #address-cells = <0>; slave { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; }; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi index 607cec2df861..20aed3946214 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi @@ -8,7 +8,6 @@ / { model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; memory@80000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts index 6f9878f124c4..4f99044837f8 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts @@ -392,7 +392,7 @@ }; &gpio0 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; input; @@ -401,7 +401,7 @@ }; &gpio3 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index acccf9a3c898..597f20be82f1 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -158,8 +158,8 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, <&edma1 1 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 13>, <&edma1 1 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -172,8 +172,8 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, <&edma1 1 15>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 15>, <&edma1 1 14>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,9 +529,8 @@ clocks = <&clks VF610_CLK_DSPI2>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 10>, - <&edma1 0 11>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 11>, <&edma1 0 10>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -544,8 +543,8 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, <&edma1 0 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 13>, <&edma1 0 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -725,13 +724,13 @@ clocks = <&clks VF610_CLK_CAAM>; clock-names = "ipg"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 3bce5876a9d8..4f002aa7fbaf 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -754,6 +754,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index d7c0a9574ce8..b1e20579e071 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -268,6 +268,7 @@ &scifa0 { pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index f746f0b9e686..4f97c09dbc9f 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -227,6 +227,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -265,6 +266,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -374,6 +376,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -395,6 +398,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -412,6 +416,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1948,6 +1953,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -2018,5 +2024,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e4e1d9c98c61..e9f90fa44d55 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -679,6 +679,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 08381498350a..f518eadd8b9c 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -312,6 +312,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index e57567adff55..5023b41c28b3 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -125,6 +125,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -152,6 +153,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -291,6 +293,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -312,6 +315,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -323,6 +327,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7791-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1875,6 +1880,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1945,5 +1951,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index a3986076d8e3..23ec0f8a6651 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -301,6 +301,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts index bfc780f7e396..93bd81723c8f 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -183,6 +183,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 08cbe6c13cee..7513afc1c958 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -82,6 +82,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; lbsc: bus { @@ -109,6 +110,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -308,6 +310,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -318,6 +321,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -329,6 +333,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -947,6 +952,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 2c05d7c2b377..45b267ec2679 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -642,6 +642,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index e48e43cc6b03..fc6d3bcca296 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -117,6 +117,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -137,6 +138,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -276,6 +278,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; /* Special CPG clocks */ @@ -287,6 +290,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -298,6 +302,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7793-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1454,6 +1459,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1524,5 +1530,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index f70e26aa83a0..3f06a7f67d62 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -479,6 +479,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 2a0819311a3c..342825605768 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -394,6 +394,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index bc16c896c0f9..92010d09f6c4 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -99,6 +99,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -119,6 +120,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -243,6 +245,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -253,6 +256,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -264,6 +268,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7794-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1440,6 +1445,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1491,5 +1497,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 7548291c8d7e..87e03446fb4d 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -211,8 +211,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,8 +224,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,8 +237,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,8 +250,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,8 +263,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index b7d5d305cbbe..60d55516f723 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ @@ -37,8 +38,11 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-dhcor-testbench.dtb \ stm32mp151c-mecio1r0.dtb \ stm32mp151c-mect1s.dtb \ + stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp153c-lxa-fairytux2-gen1.dtb \ + stm32mp153c-lxa-fairytux2-gen2.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 087de6f09629..b57dbdce2f40 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -78,6 +78,24 @@ serial0 = &usart1; }; + leds { + compatible = "gpio-leds"; + led-usr { + gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = <KEY_HOME>; + gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 52c5baf58ab9..535cfdc4681c 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -79,13 +79,16 @@ leds { compatible = "gpio-leds"; - led-green { + led-usr2 { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { + led-usr1 { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; + led-usr3 { + gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; + }; }; gpio-keys { diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 0019d12c3d3d..8512a6e46b33 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -100,6 +100,31 @@ always-on; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -919,6 +944,16 @@ }; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DTS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts new file mode 100644 index 000000000000..663b6de1b814 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp133.dtsi" +#include "stm32mp13xc.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "Priva E-Measuringbox board"; + compatible = "pri,prihmb", "st,stm32mp133"; + + aliases { + ethernet0 = ðernet1; + mdio-gpio0 = &mdio0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + counter-0 { + compatible = "interrupt-counter"; + gpios = <&gpioa 11 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-reset { + label = "reset-button"; + linux,code = <BTN_1>; + gpios = <&gpioi 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + led-controller-0 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm2 2 1000000 1>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm1 1 1000000 1>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm1 2 1000000 1>; + }; + }; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 1>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 1>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm2 1 1000000 1>; + }; + }; + }; + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@ce000000 { + reg = <0xce000000 0x02000000>; + no-map; + }; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc_1_pins_a>; + vdda-supply = <®_3v3>; + vref-supply = <®_3v3>; + status = "okay"; +}; + +&adc1 { + status = "okay"; + + channel@0 { /* Fan current PC0*/ + reg = <0>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@11 { /* Fan voltage */ + reg = <11>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@15 { /* Supply voltage */ + reg = <15>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; +}; + +&dts { + status = "okay"; +}; + +ðernet1 { + status = "okay"; + pinctrl-0 = <ðernet1_rmii_pins_a>; + pinctrl-1 = <ðernet1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + board-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; +}; + +&{i2c1_pins_a/pins} { + pinmux = <STM32_PINMUX('D', 3, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('B', 8, AF4)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; +}; + +&{i2c1_sleep_pins_a/pins} { + pinmux = <STM32_PINMUX('D', 3, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('B', 8, ANALOG)>; /* I2C1_SDA */ +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + mmc-ddr-3_3v; + bus-width = <8>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers1 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm1: pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers4 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm2: pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +/* Fan PWM */ +&timers5 { + status = "okay"; + + pwm3: pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers2 { + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_sleep_pins_a>; + pinctrl-2 = <&usart6_idle_pins_a>; + linux,rs485-enabled-at-boot-time; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&pinctrl { + adc_1_pins_a: adc1-0 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1 in0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ADC1 in15 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1 in11 */ + }; + }; + + ethernet1_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>; /* ETH1_RMII_REF_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet1_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + + pwm1_pins_a: pwm1-0 { + pins { + pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ + <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ + <STM32_PINMUX('E', 13, AF1)>; /* TIM1_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ + <STM32_PINMUX('E', 13, ANALOG)>; /* TIM1_CH3 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF2)>, /* TIM4_CH1 */ + <STM32_PINMUX('B', 7, AF2)>, /* TIM4_CH2 */ + <STM32_PINMUX('D', 14, AF2)>; /* TIM4_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* TIM4_CH1 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* TIM4_CH2 */ + <STM32_PINMUX('D', 14, ANALOG)>; /* TIM4_CH3 */ + }; + }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('E', 10, ANALOG)>; /* UART7_RX */ + }; + }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, AF7)>, /* USART6_TX */ + <STM32_PINMUX('F', 10, AF7)>; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 11, AF7)>; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>; /* USART6_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('F', 10, AF7)>; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('H', 11, AF7)>; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('F', 10, ANALOG)>, /* USART6_DE */ + <STM32_PINMUX('H', 11, ANALOG)>; /* USART6_RX */ + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 853dc21449d9..9902849ed040 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -176,7 +176,7 @@ gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", "", "", "", "DHSBC_nETH1_RST", - "", "DHCOR_HW-CODING_0", "", ""; + "", "DHCOR_HW-CODING_0", "", "DHSBC_HW-CODE_2"; }; &gpiob { @@ -197,7 +197,7 @@ gpio-line-names = "", "", "", "", "", "DHCOR_RAM-CODING_0", "", "", "", "DHCOR_RAM-CODING_1", "", "", - "", "", "", ""; + "", "DHSBC_HW-CODE_1", "", ""; }; &gpioe { @@ -221,6 +221,13 @@ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; }; +&gpioh { + gpio-line-names = "", "", "", "DHSBC_HW-CODE_0", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + &gpioi { gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", @@ -296,6 +303,9 @@ st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; + interrupt-parent = <&gpioe>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; spi-max-frequency = <24000000>; }; }; @@ -419,3 +429,19 @@ type = "micro"; }; }; + +/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c8..40605ea85ee1 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -26,6 +26,13 @@ }; /omit-if-no-ref/ + adc1_in10_pins_a: adc1-in10-0 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; + }; + }; + + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ @@ -585,6 +592,43 @@ }; /omit-if-no-ref/ + ethernet0_rmii_pins_d: rmii-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + ethernet0_rmii_sleep_pins_d: rmii-sleep-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -726,6 +770,25 @@ }; /omit-if-no-ref/ + i2c1_pins_c: i2c1-2 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_c: i2c1-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */ + }; + }; + + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ @@ -820,6 +883,27 @@ }; /omit-if-no-ref/ + i2s1_pins_a: i2s1-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, AF5)>, /* I2S2_SDI */ + <STM32_PINMUX('A', 4, AF5)>, /* I2S2_WS */ + <STM32_PINMUX('A', 5, AF5)>; /* I2S2_CK */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + i2s1_sleep_pins_a: i2s1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, ANALOG)>, /* I2S2_SDI */ + <STM32_PINMUX('A', 4, ANALOG)>, /* I2S2_WS */ + <STM32_PINMUX('A', 5, ANALOG)>; /* I2S2_CK */ + }; + }; + + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ @@ -1419,6 +1503,23 @@ }; /omit-if-no-ref/ + pwm1_pins_d: pwm1-3 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm1_sleep_pins_d: pwm1-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; + }; + }; + + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -2161,6 +2262,66 @@ }; /omit-if-no-ref/ + sdmmc2_b4_pins_c: sdmmc2-b4-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_c: sdmmc2-b4-od-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_c: sdmmc2-b4-sleep-2 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -2390,6 +2551,66 @@ }; /omit-if-no-ref/ + sdmmc3_b4_pins_c: sdmmc3-b4-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_c: sdmmc3-b4-od-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_c: sdmmc3-b4-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ @@ -2601,6 +2822,41 @@ }; /omit-if-no-ref/ + uart4_pins_e: uart4-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_e: uart4-idle-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_e: uart4-sleep-4 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ @@ -2678,6 +2934,23 @@ }; /omit-if-no-ref/ + uart7_pins_d: uart7-3 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>, /* UART7_TX */ + <STM32_PINMUX('F', 8, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('F', 9, AF7)>; /* UART7_CTS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -3119,6 +3392,25 @@ }; /omit-if-no-ref/ + i2c6_pins_b: i2c6-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, AF2)>, /* I2C6_SCL */ + <STM32_PINMUX('A', 12, AF2)>; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c6_sleep_pins_b: i2c6-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C6_SCL */ + <STM32_PINMUX('A', 12, ANALOG)>; /* I2C6_SDA */ + }; + }; + + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts new file mode 100644 index 000000000000..39a3211c6133 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include <arm/st/stm32mp151.dtsi> +#include <arm/st/stm32mp15xc.dtsi> +#include <arm/st/stm32mp15-pinctrl.dtsi> +#include <arm/st/stm32mp15xxad-pinctrl.dtsi> +#include <arm/st/stm32mp15-scmi.dtsi> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Plymovent AQM board"; + compatible = "ply,plyaqm", "st,stm32mp151"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart7; + }; + + codec { + compatible = "invensense,ics43432"; + + port { + codec_endpoint: endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; /* WHITE_EN */ + color = <LED_COLOR_ID_WHITE>; + default-state = "on"; + }; + }; + + v3v3: fixed-regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v_sw: fixed-regulator-v5sw { + compatible = "regulator-fixed"; + regulator-name = "5v-switched"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioe 10 GPIO_ACTIVE_HIGH>; /* 5V_SWITCHED_EN */ + startup-delay-us = <100000>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@cfd00000 { + reg = <0xcfd00000 0x300000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15"; + dais = <&i2s1_port>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; /* WLAN_REG_ON */ + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in10_pins_a>; + vdda-supply = <&v3v3>; + vref-supply = <&v3v3>; + status = "okay"; + + adc@0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@10 { /* NTC */ + reg = <10>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; + status = "okay"; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rmii_pins_d>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_d>; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + /* KSZ8081RNA PHY */ + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpiob 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_PL_N", "HWID_CP", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "LED_LATCH", "", + "", "RELAY1_EN", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_Q7", "", ""; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "RELAY2_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "SW1", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_c>; + pinctrl-1 = <&i2c1_sleep_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&i2c6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_b>; + pinctrl-1 = <&i2c6_sleep_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clocks = <&scmi_clk CK_SCMI_I2C6>; + resets = <&scmi_reset RST_SCMI_I2C6>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pressure-sensor@47 { + compatible = "bosch,bmp580"; + reg = <0x47>; + vdda-supply = <&v5v_sw>; + vddd-supply = <&v5v_sw>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + vdd-supply = <&v5v_sw>; + }; + + pm-sensor@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; + }; +}; + +&i2s1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s1_pins_a>; + pinctrl-1 = <&i2s1_sleep_pins_a>; + clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + #clock-cells = <0>; /* Set I2S2 as master clock provider */ + status = "okay"; + + i2s1_port: port { + i2s1_endpoint: endpoint { + format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_endpoint>; + }; + }; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status = "okay"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; + status = "okay"; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_c &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_c &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_c &sdmmc2_d47_sleep_pins_b>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_c>; + pinctrl-1 = <&sdmmc3_b4_od_pins_c>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_c>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&timers5 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm { + pinctrl-0 = <&pwm1_pins_d>; + pinctrl-1 = <&pwm1_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_e>; + pinctrl-1 = <&uart4_idle_pins_e>; + pinctrl-2 = <&uart4_sleep_pins_e>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_d>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; /* BT_REG_ON */ + max-speed = <4000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; /* BT_HOST_WAKE */ + interrupt-names = "host-wakeup"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts new file mode 100644 index 000000000000..3a0e84262424 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 1"; + compatible = "lxa,stm32mp153c-fairytux2-gen1", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = <KEY_ESC>; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = <KEY_HOME>; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "GPIO3", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "LED2_GK_YA", + "RS485_EN", "RS485_120R", "", "CAN_120R"; + }; +}; + +&led_controller_io { + /* + * led-2 and led-3 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO1 ---+---|led-2|>--+--- GPIO3 + * +--<|led-3|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart3 { + /* + * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well, + * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same + * interrupt and only one of them can be used at a time. + */ + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts new file mode 100644 index 000000000000..66e6da912508 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 2"; + compatible = "lxa,stm32mp153c-fairytux2-gen2", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = <KEY_ESC>; + gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = <KEY_HOME>; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "GPIO1", "GPIO_INT", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "GPIO2", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpioh>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&board_tca6408_pins>; + #interrupt-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "USB_CC_ALERT", + "RS485_EN", "RS485_120R", "USB_CC_RESET", "CAN_120R"; + }; + + usb_c: typec@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupt-parent = <&io_board_gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_5v>; + vsys-supply = <&v3v3_hdmi>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + /* + * The sensor itself is powered by a voltage divider from the + * always-on 5V supply. + * The required pull-up resistors however are on v3v3_hdmi. + */ + vs-supply = <&v3v3_hdmi>; + }; + + io_board_eeprom: eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + vcc-supply = <&v3v3_hdmi>; + }; +}; + +&rtc { + status = "okay"; +}; + +&led_controller_io { + led-2 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&usart3 { + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + usb-role-switch; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; +}; + +&pinctrl { + board_tca6408_pins: stusb1600-0 { + pins { + pinmux = <STM32_PINMUX('H', 13, GPIO)>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi new file mode 100644 index 000000000000..9eeb9d6b5eb0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + can0 = &m_can1; + ethernet0 = ðernet0; + i2c0 = &i2c1; + i2c1 = &i2c4; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + spi0 = &spi4; + }; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + led-controller-cpu { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + led_controller_io: led-controller-io { + compatible = "gpio-leds"; + + /* + * led-0 and led-1 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO0 ---+---|led-0|>--+--- GPIO2 + * +--<|led-1|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "LCD_TE", "", "", /* 5 */ + "LCD_DC", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioe { + gpio-line-names = "LCD_CS", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; + termination-gpios = <&io_board_gpio 7 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "external"; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + regulator-enable-ramp-delay = <1000>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 5f9c0160a9c4..324f7bb988d1 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -67,7 +67,7 @@ touchscreen@38 { compatible = "focaltech,ft6236"; reg = <0x38>; - interrupts = <2 2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; diff --git a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts index 4df10379ff22..173401c58d53 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts @@ -412,14 +412,14 @@ status = "okay"; /* Don't pull down battery voltage adc io channel */ - batt_volt_en { + batt-volt-en-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; }; /* Don't impede Bluetooth clock signal */ - bt_clock_en { + bt-clock-en-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; @@ -433,19 +433,19 @@ * anything, but they are present in the source code from LEGO. */ - bt_pic_en { + bt-pic-en-hog { gpio-hog; gpios = <51 GPIO_ACTIVE_HIGH>; output-low; }; - bt_pic_rst { + bt-pic-rst-hog { gpio-hog; gpios = <78 GPIO_ACTIVE_HIGH>; output-high; }; - bt_pic_cts { + bt-pic-cts-hog { gpio-hog; gpios = <87 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi index e27837093e43..70e33cdd519a 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi @@ -205,7 +205,7 @@ /* T2_GPIO_2 low to route GPIO_61 to on-board devices */ &twl_gpio { - en_on_board_gpio_61 { + en-on-board-gpio-61-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 3fcef3080eae..150dd84c9e0f 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -1414,7 +1414,7 @@ uart3: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1765,7 +1765,7 @@ uart1: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1794,7 +1794,7 @@ uart2: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1823,7 +1823,7 @@ uart4: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts index 8fd076e5d1b0..4b8bfd0188ad 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts @@ -7,6 +7,11 @@ #include "omap443x.dtsi" #include "omap4-panda-common.dtsi" +/ { + model = "TI OMAP4 PandaBoard (A4)"; + compatible = "ti,omap4-panda-a4", "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; + /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi index a7db3f3009f2..153b8d93cbee 100644 --- a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -8,6 +8,13 @@ #size-cells = <1>; compatible = "xlnx,zynq-7000"; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x3000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -34,7 +41,7 @@ }; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; @@ -93,6 +100,7 @@ }; amba: axi { + bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -190,6 +198,17 @@ reg = <0xf8006000 0x1000>; }; + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; @@ -277,13 +296,18 @@ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + }; + nor0: flash@1,0 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; }; }; @@ -308,12 +332,14 @@ }; slcr: slcr@f8000000 { + bootph-all; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + bootph-all; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0>; @@ -398,6 +424,7 @@ }; scutimer: timer@f8f00600 { + bootph-all; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/boot/dts/xilinx/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts index 8b9ab9bba23b..f5525c048426 100644 --- a/arch/arm/boot/dts/xilinx/zynq-cc108.dts +++ b/arch/arm/boot/dts/xilinx/zynq-cc108.dts @@ -18,6 +18,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart0; + spi0 = &qspi; }; chosen { @@ -48,7 +49,44 @@ ethernet_phy: ethernet-phy@1 { reg = <1>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { /* 16 MB */ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot-bs"; + reg = <0x0 0x400000>; /* 4MB */ + }; + partition@400000 { + label = "qspi-linux"; + reg = <0x400000 0x400000>; /* 4MB */ + }; + partition@800000 { + label = "qspi-rootfs"; + reg = <0x800000 0x400000>; /* 4MB */ + }; + partition@c00000 { + label = "qspi-devicetree"; + reg = <0xc00000 0x100000>; /* 1MB */ + }; + partition@d00000 { + label = "qspi-scratch"; + reg = <0xd00000 0x200000>; /* 2MB */ + }; + partition@f00000 { + label = "qspi-uboot-env"; + reg = <0xf00000 0x100000>; /* 1MB */ + }; }; }; @@ -59,6 +97,7 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts index 53fa6dbfd8fd..14f644156a6f 100644 --- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts +++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts @@ -51,6 +51,8 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-microzed.dts b/arch/arm/boot/dts/xilinx/zynq-microzed.dts index 6ed84fb15902..68b867e8369e 100644 --- a/arch/arm/boot/dts/xilinx/zynq-microzed.dts +++ b/arch/arm/boot/dts/xilinx/zynq-microzed.dts @@ -11,8 +11,9 @@ compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { - ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -35,6 +36,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -46,10 +52,12 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-parallella.dts b/arch/arm/boot/dts/xilinx/zynq-parallella.dts index 54592aeb92b9..366af4fcf8d9 100644 --- a/arch/arm/boot/dts/xilinx/zynq-parallella.dts +++ b/arch/arm/boot/dts/xilinx/zynq-parallella.dts @@ -46,7 +46,6 @@ compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22"; reg = <0>; - device_type = "ethernet-phy"; marvell,reg-init = <0x3 0x10 0xff00 0x1e>, <0x3 0x11 0xfff0 0xa>; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts index 6efdbca9d3ef..6955637c5b1a 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -15,7 +15,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -63,19 +66,6 @@ }; }; -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - &can0 { status = "okay"; pinctrl-names = "default"; @@ -95,7 +85,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -152,7 +141,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -174,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -210,7 +199,7 @@ conf { groups = "can0_9_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -233,7 +222,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -256,7 +245,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -274,7 +263,7 @@ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -298,11 +287,11 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; @@ -311,7 +300,7 @@ conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -324,7 +313,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -338,7 +327,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -351,7 +340,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -364,7 +353,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -387,7 +376,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -403,13 +392,53 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts index 77943c16d33f..3b803c698473 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc706.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc706.dts @@ -14,7 +14,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -46,7 +49,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -100,7 +102,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -122,7 +124,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -150,7 +152,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -173,7 +175,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -187,7 +189,7 @@ conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -211,7 +213,7 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -224,7 +226,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -238,7 +240,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -251,7 +253,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -264,7 +266,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -287,7 +289,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -303,13 +305,54 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts index 0dd352289a45..5fe799c3c7cf 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts @@ -15,6 +15,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; spi1 = &spi1; }; @@ -45,7 +46,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -57,7 +57,43 @@ compatible = "atmel,24c02"; reg = <0x52>; }; +}; +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; }; &sdhci0 { @@ -85,6 +121,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts index 56732e8f6ca1..f9a086fe66d3 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts @@ -47,6 +47,36 @@ }; }; +&nfc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + nand@0 { + reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nand-fsbl-uboot"; + reg = <0x0 0x1000000>; + }; + partition@1000000 { + label = "nand-linux"; + reg = <0x1000000 0x2000000>; + }; + partition@3000000 { + label = "nand-rootfs"; + reg = <0x3000000 0x200000>; + }; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -54,6 +84,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts index d2359b789eb8..24520e7d3965 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts @@ -53,6 +53,40 @@ }; }; +&nor0 { + status = "okay"; + bank-width = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "nor-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "nor-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi1 { status = "okay"; num-cs = <4>; @@ -60,5 +94,6 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts index 38d96adc870c..103e87ea7253 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts @@ -15,6 +15,7 @@ ethernet0 = &gem1; i2c0 = &i2c1; serial0 = &uart0; + spi0 = &qspi; spi1 = &spi0; }; @@ -40,7 +41,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -58,6 +58,44 @@ }; }; +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -73,5 +111,6 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zed.dts b/arch/arm/boot/dts/xilinx/zynq-zed.dts index 6a5a93aa6552..52ba569b2b9f 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zed.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zed.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -43,15 +44,55 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi index 33b02e05ce82..defef9c8da13 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi @@ -63,6 +63,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -73,14 +78,17 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts index 7b87e10d3953..56b917eec783 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts @@ -10,6 +10,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -49,15 +51,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo.dts b/arch/arm/boot/dts/xilinx/zynq-zybo.dts index 755f6f109d5a..fbc7d1b12e94 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zybo.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zybo.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -44,15 +45,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..8b76821f190f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -321,6 +321,10 @@ config ARCH_STM32 help This enables support for ARMv8 based STMicroelectronics STM32 family, including: + - STM32MP21: + - STM32MP211, STM32MP213, STM32MP215. + - STM32MP23: + - STM32MP231, STM32MP233, STM32MP235. - STM32MP25: - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. @@ -374,13 +378,12 @@ config ARCH_UNIPHIER This enables support for Socionext UniPhier SoC family. config ARCH_VEXPRESS - bool "ARMv8 software model (Versatile Express)" + bool "ARM Ltd Platforms" select GPIOLIB select PM select PM_GENERIC_DOMAINS help - This enables support for the ARMv8 software model (Versatile - Express). + This enables support for the ARM Ltd Platforms. config ARCH_VISCONTI bool "Toshiba Visconti SoC Family" diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts index cf58e43dd5b2..d53b72d18242 100644 --- a/arch/arm64/boot/dts/airoha/en7581-evb.dts +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -24,3 +24,47 @@ reg = <0x0 0x80000000 0x2 0x00000000>; }; }; + +&spi_nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootloader@0 { + label = "bootloader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + art@200000 { + label = "art"; + reg = <0x00200000 0x00400000>; + }; + + tclinux@600000 { + label = "tclinux"; + reg = <0x00600000 0x03200000>; + }; + + tclinux_slave@3800000 { + label = "tclinux_alt"; + reg = <0x03800000 0x03200000>; + }; + + rootfs_data@6a00000 { + label = "rootfs_data"; + reg = <0x06a00000 0x01400000>; + }; + + reserved_bmt@7e00000 { + label = "reserved_bmt"; + reg = <0x07e00000 0x00200000>; + read-only; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index 55eb1762fb11..26b136940917 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -2,6 +2,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/en7523-clk.h> +#include <dt-bindings/reset/airoha,en7581-reset.h> / { interrupt-parent = <&gic>; @@ -122,6 +124,12 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + clk20m: clock-20000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -142,6 +150,36 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x160>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + scuclk: clock-controller@1fb00000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fb00000 0x0 0x970>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart1: serial@1fbf0000 { compatible = "ns16550"; reg = <0x0 0x1fbf0000 0x0 0x30>; @@ -150,5 +188,58 @@ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <1843200>; }; + + rng@1faa1000 { + compatible = "airoha,en7581-trng"; + reg = <0x0 0x1faa1000 0x0 0xc04>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + }; + + system-controller@1fbf0200 { + compatible = "airoha,en7581-gpio-sysctl", "syscon", + "simple-mfd"; + reg = <0x0 0x1fbf0200 0x0 0xc0>; + + en7581_pinctrl: pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + i2c0: i2c@1fbf8000 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8000 0x0 0x100>; + + resets = <&scuclk EN7581_I2C2_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@1fbf8100 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8100 0x0 0x100>; + + resets = <&scuclk EN7581_I2C_MASTER_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts index a387bccdcefd..a7e3be0155a8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -38,6 +39,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &pio { vcc-pb-supply = <®_dcdc1>; vcc-pc-supply = <®_eldo1>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi new file mode 100644 index 000000000000..c6a2efa037dc --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com> + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-a100-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-408000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-600000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <600000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1020000>; + opp-microvolt-speed1 = <980000>; + opp-microvolt-speed2 = <950000>; + }; + + opp-1200000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1200000000>; + + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp-1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1060000>; + opp-microvolt-speed2 = <1030000>; + }; + + opp-1464000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1464000000>; + + opp-microvolt-speed0 = <1180000>; + opp-microvolt-speed1 = <1180000>; + opp-microvolt-speed2 = <1130000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index a24adba201af..f9f6fea03b74 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -23,6 +23,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu1: cpu@1 { @@ -30,6 +31,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu2: cpu@2 { @@ -37,6 +39,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu3: cpu@3 { @@ -44,6 +47,7 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; }; @@ -175,6 +179,10 @@ ths_calibration: calib@14 { reg = <0x14 8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x2>; + }; }; watchdog@30090a0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index a231abf1684a..7e17ca07892d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -167,6 +167,12 @@ gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ default-state = "on"; }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; /* PI11 */ + }; }; reg_vcc5v: regulator-vcc5v { /* USB-C power input */ @@ -237,6 +243,7 @@ battery_power: battery-power { compatible = "x-powers,axp717-battery-power-supply"; monitored-battery = <&battery>; + x-powers,no-thermistor; }; regulators { @@ -328,8 +335,17 @@ regulator-name = "boost"; }; + /* + * Regulator function is unknown, but reading + * GPIO values in bootloader is inconsistent + * on reboot if this is disabled. Setting to + * default value from regulator OTP mem. + */ reg_cpusldo: cpusldo { - /* unused */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts index ff453336eab1..bef4d107482f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -71,6 +71,25 @@ <&pio 8 2 GPIO_ACTIVE_LOW>; #mux-control-cells = <0>; }; + + reg_vcc3v8_usb: regulator-vcc3v8-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 4 5 GPIO_ACTIVE_HIGH>; /* PE5 */ + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc3v8-usb"; + }; + + reg_vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0-usb"; + vin-supply = <®_vcc3v8_usb>; + }; }; &gpadc { @@ -113,3 +132,7 @@ function = "gpio_out"; }; }; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0_usb>; +}; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts index 7c82d90e940d..8862adae44e9 100644 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts @@ -58,7 +58,7 @@ &spi1 { status = "okay"; - sdcard0: sdcard@0 { + sdcard0: mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts index 58e2b0a6f841..b34dd8d5d1b1 100644 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts @@ -8,32 +8,10 @@ /dts-v1/; -/include/ "amd-seattle-soc.dtsi" -/include/ "amd-seattle-cpus.dtsi" +/include/ "amd-overdrive-rev-b0.dts" / { model = "AMD Seattle (Rev.B1) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "okay"; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "okay"; }; &gpio2 { @@ -44,48 +22,11 @@ status = "okay"; }; -&gpio4 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - &sata1 { status = "okay"; }; -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - &ipmi_kcs { status = "okay"; }; -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi index 2dd2c28171ee..73f687773ce6 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi @@ -5,51 +5,39 @@ * Copyright (C) 2014 Advanced Micro Devices, Inc. */ - adl3clk_100mhz: clk100mhz_0 { + adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "adl3clk_100mhz"; }; - ccpclk_375mhz: clk375mhz { + ccpclk_375mhz: clock-375000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <375000000>; clock-output-names = "ccpclk_375mhz"; }; - sataclk_333mhz: clk333mhz { + sataclk_333mhz: clock-333000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <333000000>; clock-output-names = "sataclk_333mhz"; }; - pcieclk_500mhz: clk500mhz_0 { + dmaclk_500mhz: pcieclk_500mhz: clock-500000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <500000000>; clock-output-names = "pcieclk_500mhz"; }; - dmaclk_500mhz: clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - miscclk_250mhz: clk250mhz_4 { + xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz: + miscclk_250mhz: clock-250000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; clock-output-names = "miscclk_250mhz"; }; - uartspiclk_100mhz: clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - }; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index d3d931eb7677..a611f8288b3e 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -11,6 +11,8 @@ #address-cells = <2>; #size-cells = <2>; + /include/ "amd-seattle-clks.dtsi" + gic0: interrupt-controller@e1101000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; interrupt-controller; @@ -38,7 +40,7 @@ <1 10 0xff04>; }; - smb0: smb { + smb0: bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -51,8 +53,6 @@ */ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - /include/ "amd-seattle-clks.dtsi" - sata0: sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0 0xe0300000 0 0xf0000>; @@ -121,7 +121,6 @@ status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1020000 0 0x1000>; - spi-controller; interrupts = <0 330 4>; clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; clock-names = "sspclk", "apb_pclk"; @@ -131,7 +130,6 @@ status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1030000 0 0x1000>; - spi-controller; interrupts = <0 329 4>; clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; clock-names = "sspclk", "apb_pclk"; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi index 9259e547e2e8..18b0c2dd1b2d 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi @@ -5,35 +5,7 @@ * Copyright (C) 2015 Advanced Micro Devices, Inc. */ - xgmacclk0_dma_250mhz: clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - }; - - xgmacclk0_ptp_250mhz: clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - }; - - xgmacclk1_dma_250mhz: clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - }; - - xgmacclk1_ptp_250mhz: clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - }; - - xgmac0: xgmac@e0700000 { + xgmac0: ethernet@e0700000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0700000 0 0x80000>, <0 0xe0780000 0 0x80000>, @@ -59,7 +31,7 @@ dma-coherent; }; - xgmac1: xgmac@e0900000 { + xgmac1: ethernet@e0900000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0900000 0 0x80000>, <0 0xe0980000 0 0x80000>, diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi index de10e7aebf21..a06838552f21 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -48,3 +48,24 @@ }; }; }; + +&apb { + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,a4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + + gpio_ao_intc: interrupt-controller@8e72c { + compatible = "amlogic,a4-gpio-ao-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x8e72c 0x0 0x0c>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <140 141>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi index 17a6316de891..32ed1776891b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -48,3 +48,15 @@ }; }; }; + +&apb { + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,a5-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index e9b22868983d..a6924d246bb1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1693,8 +1693,12 @@ }; pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x02000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -1728,8 +1732,12 @@ }; pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x07000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -1806,15 +1814,23 @@ }; pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1b000 0x0 0x20>; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1a000 0x0 0x20>; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 49b51c54013f..ab2b3f15ef19 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2060,8 +2060,11 @@ }; pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x2000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>; #pwm-cells = <3>; status = "disabled"; }; @@ -2099,8 +2102,13 @@ }; pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x7000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -2301,22 +2309,37 @@ }; pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x19000 0x0 0x20>; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x1a000 0x0 0x20>; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x1b000 0x0 0x20>; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index a457b3f4397b..9aa36f17ffa2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -346,8 +346,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -355,8 +353,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pdm { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index c779a5da7d1e..952b8d02e5c2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -284,8 +284,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -293,8 +291,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index ea51341f031b..52fbc5103e45 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -389,8 +389,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -398,8 +396,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pdm { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index f70a46967e2b..5407049d2647 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -502,8 +502,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 32f98a192494..01da83658ae3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -328,8 +328,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -363,8 +361,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &uart_A { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts index 65b963d794cd..adedc1340c78 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -116,6 +116,4 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x7_pins>; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 08c33ec7e9f1..92e8b26ecccc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -257,8 +257,6 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; @@ -273,8 +271,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index d4e1990b5f26..54663c55a20e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -367,8 +367,6 @@ status = "okay"; pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_ef { @@ -380,8 +378,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index 16dd409051b4..48650bad230d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -92,16 +92,12 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi index 09d959aefb18..7e8964bacfce 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi @@ -327,16 +327,12 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 39feba7f2d08..fc05ecf90714 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -379,32 +379,24 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_ab { pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index 4cb6930ffb19..a7a0fc264cdc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -304,24 +304,18 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index d38c3a224fbe..2da49cfbde77 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -345,24 +345,18 @@ &pwm_AO_ab { pinctrl-0 = <&pwm_ao_a_3_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ab { pinctrl-0 = <&pwm_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 45ccddd1aaf0..6da1316d97c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -240,8 +240,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 2673f0dbafe7..7d99ca44e660 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -329,14 +329,14 @@ }; pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x08550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x08650 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -351,7 +351,7 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x086c0 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -498,7 +498,7 @@ }; pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x00550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index cf2e2ef81680..2ecc6ebd5a43 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -298,8 +298,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 7d7dde93fff3..c09da40ff7b0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -241,8 +241,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 1736bd2e96e2..6f67364fd63f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -150,8 +150,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 3807a184810b..6ff567225fee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -222,8 +222,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index deb295227189..bfedfc1472ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -185,8 +185,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ed00e67e6923..8ebce7114a60 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -739,6 +739,31 @@ }; }; +&pwm_ab { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_AO_ab { + clocks = <&xtal>, <&clkc CLKID_CLK81>; +}; + +&pwm_cd { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_ef { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + &pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index c5e2306ad7a4..ca7c4e8e7cac 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -280,8 +280,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* This is connected to the Bluetooth module: */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 2b94b6e5285e..4ca90ac947b7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -116,8 +116,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts index 89fe5110f7a2..62a2da766a00 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts @@ -115,8 +115,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* SD card */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index a80f0ea2773b..4e89d6f6bb57 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -211,8 +211,6 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; }; &pwm_ef { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts index c79f9f2099bf..236cedec9f19 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -145,8 +145,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi index b52a830efcce..05a0d4de3ad7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi @@ -101,8 +101,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index f58d1790de1c..2dc2fdaecf9f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -809,6 +809,31 @@ }; }; +&pwm_ab { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_AO_ab { + clocks = <&xtal>, <&clkc CLKID_CLK81>; +}; + +&pwm_cd { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_ef { + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + &pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 96a3dd2d8a99..2a09b3d550e2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -289,16 +289,12 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &sd_emmc_a { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 7356d3b628b1..ecaf678b23dd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -192,8 +192,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi index 929e4720ae76..ac9c4c2673b1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi @@ -458,24 +458,18 @@ status = "okay"; pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_b_x7_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_d_x3_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi index d1fa8b8bf795..a3463149db3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -199,15 +199,11 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -215,8 +211,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 81dce862902a..40db95f64636 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -367,8 +367,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 9c0b544e2209..5d75ad3f3e46 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -78,8 +78,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index 7b0e9817a615..ad8d07883760 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -392,8 +392,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 2e3397e55da2..37d7f64b6d5d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -435,15 +435,11 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -451,8 +447,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index ab6ebb53218a..4f337bff36cd 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -46,6 +46,22 @@ dtb-$(CONFIG_ARCH_APPLE) += t8011-j120.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j121.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j207.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j208.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j132.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j137.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j140a.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j140k.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j152f.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j160.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j174.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j185.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j185f.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j213.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j215.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j223.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j230k.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j214k.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j680.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8012-j780.dtb dtb-$(CONFIG_ARCH_APPLE) += t8015-d201.dtb dtb-$(CONFIG_ARCH_APPLE) += t8015-d20.dtb dtb-$(CONFIG_ARCH_APPLE) += t8015-d211.dtb diff --git a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi index 0b16adf07f79..8868df1538d6 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { @@ -49,3 +50,11 @@ }; }; }; + +&dwi_bl { + status = "okay"; +}; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi index 741c5a9f21dd..dd57eb1d34c0 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8965x-opp.dtsi" #include <dt-bindings/input/input.h> / { @@ -49,3 +50,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi index b27ef5680626..f3696d22e71c 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { @@ -49,3 +50,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi new file mode 100644 index 000000000000..e4d568c4a119 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz + * + * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/ { + cyclone_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <15500>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <43000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <26000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <30000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <39500>; + }; + opp06 { + opp-hz = /bits/ 64 <1296000000>; + opp-level = <6>; + clock-latency-ns = <45500>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi b/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi new file mode 100644 index 000000000000..da265f484307 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S5L8960X "A7" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_secuart0: power-controller@200f0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "secuart0"; + power-domains = <&ps_sio_p>; + }; + + ps_secuart1: power-controller@200f8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "secuart1"; + power-domains = <&ps_sio_p>; + }; + + ps_cpm: power-controller@20010 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_lio: power-controller@20018 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20020 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20028 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20030 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20038 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20038 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20040 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20048 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20050 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20058 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20060 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20060 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20068 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20068 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20070 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20070 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20078 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20078 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20080 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20080 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20088 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20088 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20090 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20090 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20098 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20098 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@200a0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@200a8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@200b0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@200b8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@200c0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@200c8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@200d0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@200d8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@200e0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@200e8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_sio_p: power-controller@20110 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_usb: power-controller@20158 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20160 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20170 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20180 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@201a8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_media: power-controller@201d8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@201d0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@201e0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@201e8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@201b0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_aes0: power-controller@20100 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@20108 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@20118 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host0>; + }; + + ps_hsic1_phy: power-controller@20120 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host0>; + }; + + ps_hsic2_phy: power-controller@20128 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic2_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@20130 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20138 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20140 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Core device */ + }; + + ps_mcu: power-controller@20148 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20150 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20168 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@20178 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1_ohci"; + power-domains = <&ps_usb2host1>; + }; + + ps_usbotg: power-controller@20188 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20190 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20198 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@201a0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@201b8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp_busmux>; + }; + + ps_dp: power-controller@201c0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_disp1: power-controller@201c8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp_busmux>; + }; + + ps_vdec: power-controller@201f0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@201f8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20200 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_ans_dll: power-controller@20208 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans_dll"; + power-domains = <&ps_ans>; + }; + + ps_gfx: power-controller@20218 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20268 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + power-domains = <&ps_secuart1>, <&ps_secuart0>; + apple,always-on; /* Locked on */ + }; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index 0218ecac1d83..d820b0e43050 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -33,6 +33,8 @@ compatible = "apple,cyclone"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&cyclone_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -41,6 +43,8 @@ compatible = "apple,cyclone"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&cyclone_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -53,6 +57,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0a0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0a0000 0x0 0x4000>; @@ -62,9 +72,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,s5l8960x-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -78,11 +97,20 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200010 { + compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl: pinctrl@20e300000 { compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -111,3 +139,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "s5l8960x-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi b/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi new file mode 100644 index 000000000000..d34dae74a90c --- /dev/null +++ b/arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz + * + * target-type: J71, J72, J73 + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/ { + cyclone_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <10000>; + }; + opp02 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <3>; + clock-latency-ns = <30000>; + }; + opp04 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <4>; + clock-latency-ns = <39500>; + }; + opp05 { + opp-hz = /bits/ 64 <1296000000>; + opp-level = <5>; + clock-latency-ns = <45500>; + }; + opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <46500>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi b/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi index 4276bd890e81..cb42c5f2c1b6 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3-common.dtsi @@ -43,6 +43,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi b/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi new file mode 100644 index 000000000000..196b8e745a95 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8000/3 "A9" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80150 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80158 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80168 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80170 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80178 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80180 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80188 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80190 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80198 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80160 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@80130 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_isp_sens0: power-controller@80138 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80140 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_usb: power-controller@80250 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80258 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80260 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80270 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@80280 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@802c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@802b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_rtmux>; + }; + + ps_pmp: power-controller@802e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_uart5: power-controller@80200 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80208 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80210 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80218 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@80220 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80228 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80230 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80238 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80240 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80248 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80268 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@80278 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1_ohci"; + power-domains = <&ps_usb2host1>; + }; + + ps_usb2host2_ohci: power-controller@80288 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2_ohci"; + power-domains = <&ps_usb2host2>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_rtmux>; + }; + + ps_dp: power-controller@802c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@802f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@80308 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80310 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80318 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80320 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link0"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80328 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link1"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80330 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link2"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80338 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link3"; + power-domains = <&ps_pcie>; + }; + + ps_gfx: power-controller@80340 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@88000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_busif &ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + power-domains = <&ps_aop>; + }; + + ps_aop_cpu: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi new file mode 100644 index 000000000000..c0e9ae45627c --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8000/S8003 "A9" SoC + * + * This file contains parts common to both variants of A9 + * + * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "apple,twister"; + reg = <0x0 0x0>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "apple,twister"; + reg = <0x0 0x1>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + cpufreq: performance-controller@202220000 { + compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + serial0: serial@20a0c0000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,s8000-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200080 { + compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 208>; + apple,npins = <208>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 42>; + apple,npins = <42>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmgr_mini: power-management@210200000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + + wdt: watchdog@2102b0000 { + compatible = "apple,s8000-wdt", "apple,wdt"; + reg = <0x2 0x102b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +#include "s800-0-3-pmgr.dtsi" + +/* + * The A9 was made by two separate fabs on two different process + * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. + */ diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/apple/s8000.dtsi index 6e9046ea106c..72322f5677ab 100644 --- a/arch/arm64/boot/dts/apple/s8000.dtsi +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -4,141 +4,65 @@ * * Other names: H8P, "Maui" * - * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/apple-aic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/apple.h> +#include "s800-0-3.dtsi" / { - interrupt-parent = <&aic>; - #address-cells = <2>; - #size-cells = <2>; + twister_opp: opp-table { + compatible = "operating-points-v2"; - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,twister"; - reg = <0x0 0x0>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <650>; }; - - cpu1: cpu@1 { - compatible = "apple,twister"; - reg = <0x0 0x1>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <75000>; }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - nonposted-mmio; - ranges; - - serial0: serial@20a0c0000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x0a0c0000 0x0 0x4000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; - /* Use the bootloader-enabled clocks for now. */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <27000>; }; - - aic: interrupt-controller@20e100000 { - compatible = "apple,s8000-aic", "apple,aic"; - reg = <0x2 0x0e100000 0x0 0x100000>; - #interrupt-cells = <3>; - interrupt-controller; + opp04 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <4>; + clock-latency-ns = <32000>; }; - - pinctrl_ap: pinctrl@20f100000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x0f100000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 208>; - apple,npins = <208>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = <5>; + clock-latency-ns = <35000>; }; - - pinctrl_aop: pinctrl@2100f0000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x100f0000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <6>; + clock-latency-ns = <45000>; }; - - wdt: watchdog@2102b0000 { - compatible = "apple,s8000-wdt", "apple,wdt"; - reg = <0x2 0x102b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <7>; + clock-latency-ns = <58000>; }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt"; - /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ - interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <1844000000>; + opp-level = <8>; + clock-latency-ns = <58000>; + turbo-mode; + }; +#endif }; }; /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ diff --git a/arch/arm64/boot/dts/apple/s8001-common.dtsi b/arch/arm64/boot/dts/apple/s8001-common.dtsi index e94d0e77653a..91b06e113894 100644 --- a/arch/arm64/boot/dts/apple/s8001-common.dtsi +++ b/arch/arm64/boot/dts/apple/s8001-common.dtsi @@ -24,6 +24,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp0>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi new file mode 100644 index 000000000000..e66a4c1c138f --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Pro (12.9-inch) + * + * This file contains parts common to iPad Pro (12.9-inch). + * + * target-type: J98a, J99a + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +&ps_dcs4 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs5 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/arch/arm64/boot/dts/apple/s8001-j98a.dts b/arch/arm64/boot/dts/apple/s8001-j98a.dts index 6d6b841e7ab0..162eca05c2d9 100644 --- a/arch/arm64/boot/dts/apple/s8001-j98a.dts +++ b/arch/arm64/boot/dts/apple/s8001-j98a.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" / { compatible = "apple,j98a", "apple,s8001", "apple,arm-platform"; diff --git a/arch/arm64/boot/dts/apple/s8001-j99a.dts b/arch/arm64/boot/dts/apple/s8001-j99a.dts index d20194b1cae7..7b765820c69e 100644 --- a/arch/arm64/boot/dts/apple/s8001-j99a.dts +++ b/arch/arm64/boot/dts/apple/s8001-j99a.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" / { compatible = "apple,j99a", "apple,s8001", "apple,arm-platform"; diff --git a/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi b/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi new file mode 100644 index 000000000000..859ab77ae92b --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi @@ -0,0 +1,822 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8001 "A9X" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80148 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80150 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pcie_ref: power-controller@80140 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80160 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80168 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80170 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80178 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80180 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80188 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80190 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@80198 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@801f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80158 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@80278 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80280 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80288 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80298 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@802a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + apple,always-on; /* Core device */ + }; + + ps_disp1mux: power-controller@802e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1mux"; + }; + + ps_disp0: power-controller@802d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_rtmux>; + }; + + ps_disp1: power-controller@802f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp1mux>; + }; + + ps_uart6: power-controller@80200 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80208 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80210 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@80218 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80230 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80238 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80240 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80248 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80250 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80258 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + }; + + ps_dcs5: power-controller@80260 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + }; + + ps_dcs6: power-controller@80268 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + }; + + ps_dcs7: power-controller@80270 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + }; + + ps_usb2host0_ohci: power-controller@80290 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@802b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@802c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp0: power-controller@802e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp0"; + power-domains = <&ps_disp0>; + }; + + ps_dp1: power-controller@802f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp1"; + power-domains = <&ps_disp1>; + }; + + ps_dpa0: power-controller@80220 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + }; + + ps_dpa1: power-controller@80228 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + }; + + ps_media: power-controller@80308 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@80300 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@80318 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@80310 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@80340 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80348 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_srs: power-controller@80390 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "srs"; + power-domains = <&ps_media>; + }; + + ps_pcie_aux: power-controller@80350 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80358 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link0"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80360 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link1"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80368 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link2"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80370 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link3"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link4: power-controller@80378 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link4"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link5: power-controller@80380 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link5"; + power-domains = <&ps_pcie>; + }; + + ps_vdec: power-controller@80330 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80388 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_pmp: power-controller@80320 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@80328 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on*/ + }; + + ps_venc_pipe: power-controller@88000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index 23ee3238844d..d56d49c048bb 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -32,6 +32,8 @@ compatible = "apple,twister"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,11 +42,62 @@ compatible = "apple,twister"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + twister_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <800>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <53000>; + }; + opp03 { + opp-hz = /bits/ 64 <792000000>; + opp-level = <3>; + clock-latency-ns = <18000>; + }; + opp04 { + opp-hz = /bits/ 64 <1080000000>; + opp-level = <4>; + clock-latency-ns = <21000>; + }; + opp05 { + opp-hz = /bits/ 64 <1440000000>; + opp-level = <5>; + clock-latency-ns = <25000>; + }; + opp06 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <6>; + clock-latency-ns = <33000>; + }; + opp07 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <7>; + clock-latency-ns = <45000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -52,6 +105,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -61,19 +120,30 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,s8000-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -95,6 +165,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -113,6 +184,14 @@ <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,s8000-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +210,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "s8001-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/s8003.dtsi b/arch/arm64/boot/dts/apple/s8003.dtsi index 7e4ad4f7e499..79df5c783260 100644 --- a/arch/arm64/boot/dts/apple/s8003.dtsi +++ b/arch/arm64/boot/dts/apple/s8003.dtsi @@ -4,18 +4,65 @@ * * Other names: H8P, "Malta" * - * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ -#include "s8000.dtsi" +#include "s800-0-3.dtsi" + +/ { + twister_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <500>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <45000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + }; + opp04 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <4>; + clock-latency-ns = <25000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = <5>; + clock-latency-ns = <28000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <6>; + clock-latency-ns = <35000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <7>; + clock-latency-ns = <38000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <1844000000>; + opp-level = <8>; + clock-latency-ns = <38000>; + turbo-mode; + }; +#endif + }; +}; /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ diff --git a/arch/arm64/boot/dts/apple/s800x-6s.dtsi b/arch/arm64/boot/dts/apple/s800x-6s.dtsi index 49b04db310c6..1dcf80cc2920 100644 --- a/arch/arm64/boot/dts/apple/s800x-6s.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-6s.dtsi @@ -47,3 +47,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi index 32570ed3cdf0..c1701e81f0c1 100644 --- a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi @@ -41,3 +41,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-se.dtsi b/arch/arm64/boot/dts/apple/s800x-se.dtsi index a1a5690e8371..deb7c7cc90f6 100644 --- a/arch/arm64/boot/dts/apple/s800x-se.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-se.dtsi @@ -47,3 +47,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi new file mode 100644 index 000000000000..3df2fd3993b5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Devicetree include for common spi-nor nvram flash. +// +// Apple uses a consistent configiguration for the nvram on all known M1* and +// M2* devices. +// +// Copyright The Asahi Linux Contributors + +/ { + aliases { + nvram = &nvram; + }; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + nvram: partition@700000 { + label = "nvram"; + /* To be filled by the loader */ + reg = <0x0 0x0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/dts/apple/t600x-common.dtsi index fa8ead699363..87dfc13d7417 100644 --- a/arch/arm64/boot/dts/apple/t600x-common.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -362,6 +362,13 @@ clock-output-names = "clkref"; }; + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index b1c875e692c8..e9b3140ba1a9 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -163,6 +163,34 @@ status = "disabled"; }; + spi1: spi@39b104000 { + compatible = "apple,t6000-spi", "apple,spi"; + reg = <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1107 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + status = "disabled"; + }; + + spi3: spi@39b10c000 { + compatible = "apple,t6000-spi", "apple,spi"; + reg = <0x3 0x9b10c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1109 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + status = "disabled"; + }; + serial0: serial@39b200000 { compatible = "apple,s5l-uart"; reg = <0x3 0x9b200000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi index b31f1a7a2b3f..1a994c3c1b79 100644 --- a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi @@ -36,6 +36,20 @@ <APPLE_PINMUX(101, 1)>; }; + spi1_pins: spi1-pins { + pinmux = <APPLE_PINMUX(10, 1)>, + <APPLE_PINMUX(11, 1)>, + <APPLE_PINMUX(32, 1)>, + <APPLE_PINMUX(33, 1)>; + }; + + spi3_pins: spi3-pins { + pinmux = <APPLE_PINMUX(52, 1)>, + <APPLE_PINMUX(53, 1)>, + <APPLE_PINMUX(54, 1)>, + <APPLE_PINMUX(55, 1)>; + }; + pcie_pins: pcie-pins { pinmux = <APPLE_PINMUX(0, 1)>, <APPLE_PINMUX(1, 1)>, diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index 2e471dfe43cf..22ebc78e120b 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -119,3 +119,5 @@ &fpwm0 { status = "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index 1e5a19e49b08..d5b985ad5679 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -126,3 +126,5 @@ &pcie0_dart_3 { status = "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t7000-6.dtsi b/arch/arm64/boot/dts/apple/t7000-6.dtsi index f60ea4a4a387..7048d7383982 100644 --- a/arch/arm64/boot/dts/apple/t7000-6.dtsi +++ b/arch/arm64/boot/dts/apple/t7000-6.dtsi @@ -48,3 +48,11 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; + +&typhoon_opp06 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-handheld.dtsi b/arch/arm64/boot/dts/apple/t7000-handheld.dtsi index 8984c9ec6cc8..7b58aa648b53 100644 --- a/arch/arm64/boot/dts/apple/t7000-handheld.dtsi +++ b/arch/arm64/boot/dts/apple/t7000-handheld.dtsi @@ -22,6 +22,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t7000-j42d.dts b/arch/arm64/boot/dts/apple/t7000-j42d.dts index 2231db6a739d..2ec9e06cc63f 100644 --- a/arch/arm64/boot/dts/apple/t7000-j42d.dts +++ b/arch/arm64/boot/dts/apple/t7000-j42d.dts @@ -20,6 +20,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; @@ -29,3 +30,7 @@ &serial6 { status = "okay"; }; + +&typhoon_opp06 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-mini4.dtsi b/arch/arm64/boot/dts/apple/t7000-mini4.dtsi index c64ddc402fda..cc235c5a0c43 100644 --- a/arch/arm64/boot/dts/apple/t7000-mini4.dtsi +++ b/arch/arm64/boot/dts/apple/t7000-mini4.dtsi @@ -49,3 +49,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; + +&typhoon_opp06 { + status = "okay"; +}; + +&typhoon_opp07 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-n102.dts b/arch/arm64/boot/dts/apple/t7000-n102.dts index 9c55d339ba4e..99eb8a2b8c73 100644 --- a/arch/arm64/boot/dts/apple/t7000-n102.dts +++ b/arch/arm64/boot/dts/apple/t7000-n102.dts @@ -46,3 +46,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi b/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi new file mode 100644 index 000000000000..5948fa7afffc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7000 "A8" SoC + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@202d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@202b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp_busmux>; + }; + + ps_dp: power-controller@202c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_venc: power-controller@20300 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi index a7cc29e84c84..85a34dc7bc01 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -33,6 +33,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -41,11 +43,55 @@ compatible = "apple,typhoon"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; }; + typhoon_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <300>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <50000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <29000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <29000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <36000>; + }; + typhoon_opp06: opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <42000>; + status = "disabled"; /* Not available on N102 */ + }; + typhoon_opp07: opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <7>; + clock-latency-ns = <49000>; + status = "disabled"; /* J96 and J97 only */ + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -53,6 +99,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -62,6 +114,7 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -74,9 +127,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart6>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,t7000-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -90,11 +152,20 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200010 { + compatible = "apple,t7000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl: pinctrl@20e300000 { compatible = "apple,t7000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -123,3 +194,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "t7000-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t7001-air2.dtsi b/arch/arm64/boot/dts/apple/t7001-air2.dtsi index 19fabd425c52..e4ec8c1977de 100644 --- a/arch/arm64/boot/dts/apple/t7001-air2.dtsi +++ b/arch/arm64/boot/dts/apple/t7001-air2.dtsi @@ -20,6 +20,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi b/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi new file mode 100644 index 000000000000..7321cfdcd189 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7001 "A8X" SoC + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@20010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_disp1_busmux: power-controller@202c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@202d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp1_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_dp: power-controller@202b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_venc: power-controller@20300 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index a76e034c85e3..8e2c67e19c41 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -35,6 +35,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -43,6 +45,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -51,11 +55,53 @@ compatible = "apple,typhoon"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; }; + typhoon_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <300>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <31000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <32000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <32000>; + }; + opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <37000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <7>; + clock-latency-ns = <41000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -63,6 +109,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -72,9 +124,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,t7000-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -88,11 +149,13 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl: pinctrl@20e300000 { compatible = "apple,t7000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -121,3 +184,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "t7001-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8010-7.dtsi b/arch/arm64/boot/dts/apple/t8010-7.dtsi index 1332fd73f50f..1913b7b2c1fe 100644 --- a/arch/arm64/boot/dts/apple/t8010-7.dtsi +++ b/arch/arm64/boot/dts/apple/t8010-7.dtsi @@ -41,3 +41,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; + +&hurricane_opp09 { + status = "okay"; +}; + +&hurricane_opp10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-common.dtsi b/arch/arm64/boot/dts/apple/t8010-common.dtsi index 6613fb57c92f..44dc968638b1 100644 --- a/arch/arm64/boot/dts/apple/t8010-common.dtsi +++ b/arch/arm64/boot/dts/apple/t8010-common.dtsi @@ -43,6 +43,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi b/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi index 81696c6e302c..1e46e4a3a7f4 100644 --- a/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi +++ b/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi @@ -42,3 +42,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_dp>; +}; + +&hurricane_opp09 { + status = "okay"; +}; + +&hurricane_opp10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-n112.dts b/arch/arm64/boot/dts/apple/t8010-n112.dts index 6e71c3cb5d92..48fdbedf74da 100644 --- a/arch/arm64/boot/dts/apple/t8010-n112.dts +++ b/arch/arm64/boot/dts/apple/t8010-n112.dts @@ -45,3 +45,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi new file mode 100644 index 000000000000..6d451088616a --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8010 "A10" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_socuvd: power-controller@80150 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "socuvd"; + }; + + ps_mca0: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_usb: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_pmp: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_uart3: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp0_be>; + }; + + ps_dp: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80318 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_busif &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi index e3d6a8354103..17e294bd7c44 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -32,6 +32,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,11 +42,89 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardware big.LITTLE switcher + * that use p-state transitions to switch between cores. + * Only one type of core can be active at a given time. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <11000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <13000>; + }; + opp04 { + opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <18000>; + }; + opp05 { + opp-hz = /bits/ 64 <756000000>; + opp-level = <5>; + clock-latency-ns = <35000>; + }; + opp06 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <6>; + clock-latency-ns = <31000>; + }; + opp07 { + opp-hz = /bits/ 64 <1356000000>; + opp-level = <7>; + clock-latency-ns = <37000>; + }; + opp08 { + opp-hz = /bits/ 64 <1644000000>; + opp-level = <8>; + clock-latency-ns = <39500>; + }; + hurricane_opp09: opp09 { + opp-hz = /bits/ 64 <1944000000>; + opp-level = <9>; + clock-latency-ns = <46000>; + status = "disabled"; /* Not available on N112 */ + }; + hurricane_opp10: opp10 { + opp-hz = /bits/ 64 <2244000000>; + opp-level = <10>; + clock-latency-ns = <56000>; + status = "disabled"; /* Not available on N112 */ + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + hurricane_opp11: opp11 { + opp-hz = /bits/ 64 <2340000000>; + opp-level = <11>; + clock-latency-ns = <56000>; + turbo-mode; + status = "disabled"; /* Not available on N112 */ + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -52,6 +132,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -61,19 +147,37 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,t8010-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200080 { + compatible = "apple,t8010-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -95,6 +199,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -113,6 +218,14 @@ <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,t8010-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +244,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "t8010-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8011-common.dtsi b/arch/arm64/boot/dts/apple/t8011-common.dtsi index 44a0d0ea2ee3..2010b56246f1 100644 --- a/arch/arm64/boot/dts/apple/t8011-common.dtsi +++ b/arch/arm64/boot/dts/apple/t8011-common.dtsi @@ -22,6 +22,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi new file mode 100644 index 000000000000..c44e3f9d7087 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8011 "A10X" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb3host>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_usb: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2dev: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2dev"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb3host: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb3host"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb3dev: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb3dev"; + power-domains = <&ps_usbctrl>; + }; + + ps_media: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + }; + + ps_msr: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + }; + + ps_disp0_be: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_dpa: power-controller@80230 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + }; + + ps_dcs7: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + }; + + ps_smx: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_srs: power-controller@80390 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "srs"; + power-domains = <&ps_media>; + }; + + ps_pms_sram: power-controller@80308 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pmp: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pcie: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80330 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8011-pro2.dtsi b/arch/arm64/boot/dts/apple/t8011-pro2.dtsi index f4e707415003..5eaa0a73350f 100644 --- a/arch/arm64/boot/dts/apple/t8011-pro2.dtsi +++ b/arch/arm64/boot/dts/apple/t8011-pro2.dtsi @@ -40,3 +40,11 @@ }; }; }; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 6c4ed9dc4a50..5b280c896b76 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -32,6 +32,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,6 +42,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -48,11 +52,80 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardwired big.LITTLE switcher + * that use p-state transitions to switch between cores. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <12000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <135000>; + }; + opp03 { + opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <105000>; + }; + opp04 { + opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <115000>; + }; + opp05 { + opp-hz = /bits/ 64 <804000000>; + opp-level = <5>; + clock-latency-ns = <122000>; + }; + opp06 { + opp-hz = /bits/ 64 <1140000000>; + opp-level = <6>; + clock-latency-ns = <120000>; + }; + opp07 { + opp-hz = /bits/ 64 <1548000000>; + opp-level = <7>; + clock-latency-ns = <125000>; + }; + opp08 { + opp-hz = /bits/ 64 <1956000000>; + opp-level = <8>; + clock-latency-ns = <135000>; + }; + opp09 { + opp-hz = /bits/ 64 <2316000000>; + opp-level = <9>; + clock-latency-ns = <140000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp10 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <10>; + clock-latency-ns = <140000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -60,6 +133,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -69,19 +148,30 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,t8010-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -103,6 +193,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -121,6 +212,14 @@ <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,t8010-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -139,3 +238,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "t8011-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8012-j132.dts b/arch/arm64/boot/dts/apple/t8012-j132.dts new file mode 100644 index 000000000000..778a69be18dd --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j132.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,2 (j132), J132, iBridge2,4 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookPro15,2 (j132)"; + compatible = "apple,j132", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j137.dts b/arch/arm64/boot/dts/apple/t8012-j137.dts new file mode 100644 index 000000000000..dbde1ad7ce14 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j137.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMacPro1,1 (j137), J137, iBridge2,1 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMacPro1,1 (j137)"; + compatible = "apple,j137", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j140a.dts b/arch/arm64/boot/dts/apple/t8012-j140a.dts new file mode 100644 index 000000000000..5df1ff74d2df --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j140a.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,2 (j140a), J140a, iBridge2,12 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir8,2 (j140a)"; + compatible = "apple,j140a", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j140k.dts b/arch/arm64/boot/dts/apple/t8012-j140k.dts new file mode 100644 index 000000000000..a0ef1585e5c2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j140k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,1 (j140k), J140k, iBridge2,8 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir8,1 (j140k)"; + compatible = "apple,j140k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j152f.dts b/arch/arm64/boot/dts/apple/t8012-j152f.dts new file mode 100644 index 000000000000..261416eaf97e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j152f.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,1 (j152f), J152f, iBridge2,14 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,1 (j152f)"; + compatible = "apple,j152f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j160.dts b/arch/arm64/boot/dts/apple/t8012-j160.dts new file mode 100644 index 000000000000..fbcc0604f4a0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j160.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacPro7,1 (j160), J160, iBridge2,6 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacPro7,1 (j160)"; + compatible = "apple,j160", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j174.dts b/arch/arm64/boot/dts/apple/t8012-j174.dts new file mode 100644 index 000000000000..d11c70f84a71 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j174.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 Macmini8,1 (j174), J174, iBridge2,5 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 Macmini8,1 (j174)"; + compatible = "apple,j174", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j185.dts b/arch/arm64/boot/dts/apple/t8012-j185.dts new file mode 100644 index 000000000000..33492f5db46d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j185.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,1 (j185), J185, iBridge2,19 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMac20,1 (j185)"; + compatible = "apple,j185", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j185f.dts b/arch/arm64/boot/dts/apple/t8012-j185f.dts new file mode 100644 index 000000000000..3a4abdd8f7d7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j185f.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,2 (j185f), J185f, iBridge2,20 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMac20,2 (j185f)"; + compatible = "apple,j185f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j213.dts b/arch/arm64/boot/dts/apple/t8012-j213.dts new file mode 100644 index 000000000000..8270812b9a68 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j213.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,4 (j213), J213, iBridge2,10 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,4 (j213)"; + compatible = "apple,j213", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j214k.dts b/arch/arm64/boot/dts/apple/t8012-j214k.dts new file mode 100644 index 000000000000..5b8e42512060 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j214k.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,2 (j214k), J214k, iBridge2,16 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,2 (j214k)"; + compatible = "apple,j214k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j215.dts b/arch/arm64/boot/dts/apple/t8012-j215.dts new file mode 100644 index 000000000000..ad574fbf7f92 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j215.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,4 (j215), J215, iBridge2,22 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,4 (j215)"; + compatible = "apple,j215", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j223.dts b/arch/arm64/boot/dts/apple/t8012-j223.dts new file mode 100644 index 000000000000..de75d775aac5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j223.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,3 (j223), J223, iBridge2,21 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,3 (j223)"; + compatible = "apple,j223", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j230k.dts b/arch/arm64/boot/dts/apple/t8012-j230k.dts new file mode 100644 index 000000000000..4b19bc70ab0f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j230k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir9,1 (j230k), J230k, iBridge2,15 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir9,1 (j230k)"; + compatible = "apple,j230k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j680.dts b/arch/arm64/boot/dts/apple/t8012-j680.dts new file mode 100644 index 000000000000..aa5a72e07d3f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j680.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,1 (j680), J680, iBridge2,3 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,1 (j680)"; + compatible = "apple,j680", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j780.dts b/arch/arm64/boot/dts/apple/t8012-j780.dts new file mode 100644 index 000000000000..9cee891cb16d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j780.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,3 (j780), J780, iBridge2,7 + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,3 (j780)"; + compatible = "apple,j780", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi new file mode 100644 index 000000000000..36e82633bc52 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for all T2 devices + * + * target-type: J132, J137, J140a, J140k, J152f, J160, J174, J185, J185f + * J213, J214k, J215, J223, J230k, J680, J780 + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +#include "t8012.dtsi" + +/ { + chassis-type = "embedded"; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0 0>; /* To be filled by loader */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi new file mode 100644 index 000000000000..35a462edd4af --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8012 "T2" SoC + * + * Copyright (c) 2024 Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_iomux: power-controller@80150 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_gpio: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pcie_down_ref: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down_ref"; + }; + + ps_pcie_stg0_ref: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0_ref"; + }; + + ps_pcie_stg1_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_mca5: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_isp_sens0: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_pms: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_i2c4: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c5: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c5"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c6: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c6"; + power-domains = <&ps_sio_p>; + }; + + ps_usb: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_uart0: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_dpa: power-controller@80228 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80230 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp0_be>; + }; + + ps_pmp: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pcie_up_af: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up_af"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_up: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up"; + power-domains = <&ps_pcie_up_af>; + }; + + ps_venc_sys: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_ans2: power-controller@80308 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_down: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_down_aux: power-controller@80318 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down_aux"; + }; + + ps_pcie_up_aux: power-controller@80330 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up_aux"; + power-domains = <&ps_pcie_up>; + }; + + ps_pcie_stg0: power-controller@80338 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0"; + power-domains = <&ps_ans2>; + }; + + ps_pcie_stg0_aux: power-controller@80340 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0_aux"; + }; + + ps_pcie_stg1: power-controller@80348 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1"; + power-domains = <&ps_ans2>; + }; + + ps_pcie_stg1_aux: power-controller@80350 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1_aux"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_spmi: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spmi"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@80060 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80060 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_fabric: power-controller@80030 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_aon: power-controller@80088 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80088 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_debug: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_nub_sram: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_fabric: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_cpu: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_cpu"; + power-domains = <&ps_smc_fabric &ps_smc_aon>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi b/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi new file mode 100644 index 000000000000..fc4a80d0c787 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for T2 devices with a Touch Bar + * + * target-type: J152f, J213, J214k, J215, J223, J680, J780 + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +/ { + chosen { + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi new file mode 100644 index 000000000000..42df2f51ad7b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8012 "T2" SoC + * + * Other names: H9M, "Gibraltar" + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@10000 { + compatible = "apple,hurricane-zephyr"; + reg = <0x0 0x10000>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu1: cpu@10001 { + compatible = "apple,hurricane-zephyr"; + reg = <0x0 0x10001>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardware big.LITTLE switcher + * that use p-state transitions to switch between cores. + * Only one type of core can be active at a given time. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <11000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <110000>; + }; + opp04 { + opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <130000>; + }; + opp05 { + opp-hz = /bits/ 64 <756000000>; + opp-level = <5>; + clock-latency-ns = <130000>; + }; + opp06 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <6>; + clock-latency-ns = <130000>; + }; + opp07 { + opp-hz = /bits/ 64 <1356000000>; + opp-level = <7>; + clock-latency-ns = <130000>; + }; + opp08 { + opp-hz = /bits/ 64 <1644000000>; + opp-level = <8>; + clock-latency-ns = <135000>; + }; + opp09 { + opp-hz = /bits/ 64 <1944000000>; + opp-level = <9>; + clock-latency-ns = <140000>; + }; + opp10 { + opp-hz = /bits/ 64 <2244000000>; + opp-level = <10>; + clock-latency-ns = <150000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp11 { + opp-hz = /bits/ 64 <2340000000>; + opp-level = <11>; + clock-latency-ns = <150000>; + turbo-mode; + }; +#endif + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + serial0: serial@20a600000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a600000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,t8010-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + power-domains = <&ps_aic>; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 221>; + apple,npins = <221>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0100f0000 0x0 0x10000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 41>; + apple,npins = <41>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_nub: pinctrl@2111f0000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x111f0000 0x0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 19>; + apple,npins = <19>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmgr_mini: power-management@211200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x11200000 0 0x84000>; + }; + + wdt: watchdog@2112b0000 { + compatible = "apple,t8010-wdt", "apple,wdt"; + reg = <0x2 0x112b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_smc: pinctrl@212024000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x12024000 0x0 0x1000>; + power-domains = <&ps_smc_cpu>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 81>; + apple,npins = <81>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>; + /* + * SMC is not yet supported and accessing this pinctrl while SMC is + * suspended results in a hang. + */ + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +#include "t8012-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8015-8.dtsi b/arch/arm64/boot/dts/apple/t8015-8.dtsi index b6505b5185bd..0300ee1a2ffb 100644 --- a/arch/arm64/boot/dts/apple/t8015-8.dtsi +++ b/arch/arm64/boot/dts/apple/t8015-8.dtsi @@ -11,3 +11,7 @@ / { chassis-type = "handset"; }; + +&dwi_bl { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-common.dtsi b/arch/arm64/boot/dts/apple/t8015-common.dtsi index 69258a33ea50..498f58fb9715 100644 --- a/arch/arm64/boot/dts/apple/t8015-common.dtsi +++ b/arch/arm64/boot/dts/apple/t8015-common.dtsi @@ -24,6 +24,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_be &ps_mipi_dsi &ps_disp0_hilo &ps_disp0_ppp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi new file mode 100644 index 000000000000..e238c2d2732f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8015 "A11" SoC + * + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpu3: power-controller@80018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu3"; + apple,always-on; /* Core device */ + }; + + ps_cpu4: power-controller@80020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu4"; + apple,always-on; /* Core device */ + }; + + ps_cpu5: power-controller@80028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu5"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsicphy: power-controller@80128 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsicphy"; + power-domains = <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@80130 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@80138 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@80140 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_mca5: power-controller@80198 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_sio_p>; + }; + + ps_usb: power-controller@80270 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctlreg: power-controller@80278 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctlreg"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80280 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctlreg>; + }; + + ps_usb2host1: power-controller@80290 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctlreg>; + }; + + ps_rtmux: power-controller@802b0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802f0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_jpg: power-controller@802f8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802c0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_disp0_gp: power-controller@802c8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp"; + power-domains = <&ps_disp0_be>; + status = "disabled"; + }; + + ps_uart3: power-controller@80200 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80248 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80250 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs1: power-controller@80258 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs2: power-controller@80260 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs3: power-controller@80268 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_usb2host0_ohci: power-controller@80288 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2dev: power-controller@80298 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2dev"; + power-domains = <&ps_usbctlreg>; + }; + + ps_smx: power-controller@802a0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802d8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_rtmux>; + }; + + ps_dp: power-controller@802e0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_dpa: power-controller@80230 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + }; + + ps_disp0_be_2x: power-controller@802d0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be_2x"; + power-domains = <&ps_disp0_be>; + }; + + ps_isp_sys: power-controller@80350 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@80300 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_venc_sys: power-controller@80398 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_pmp: power-controller@80308 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@80310 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pcie: power-controller@80318 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80388 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_ans2: power-controller@80328 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + apple,always-on; + }; + + ps_pcie_direct: power-controller@80330 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_direct"; + apple,always-on; + }; + + ps_avd_sys: power-controller@803a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x803a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + power-domains = <&ps_media>; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_disp0_gp0: power-controller@80830 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80830 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp0"; + power-domains = <&ps_disp0_gp>; + status = "disabled"; + }; + + ps_disp0_gp1: power-controller@80838 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80838 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp1"; + status = "disabled"; + }; + + ps_disp0_ppp: power-controller@80840 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80840 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_ppp"; + }; + + ps_disp0_hilo: power-controller@80848 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80848 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_hilo"; + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_cnv: power-controller@84030 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_cnv"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_dma: power-controller@88000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + }; + + ps_venc_pipe4: power-controller@88010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop_base: power-controller@80008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80050 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_cpu: power-controller@80020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_spmi: power-controller@80058 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spmi"; + apple,always-on; /* System Power Management Interface */ + }; + + ps_smc_i2cm1: power-controller@800a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x800a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_i2cm1"; + }; + + ps_smc_fabric: power-controller@80030 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_fabric"; + }; + + ps_smc_cpu: power-controller@80140 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_cpu"; + power-domains = <&ps_smc_fabric &ps_smc_i2cm1>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 8828d830e5be..4d54afcecd50 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -58,6 +58,9 @@ compatible = "apple,mistral"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -66,6 +69,9 @@ compatible = "apple,mistral"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -74,6 +80,9 @@ compatible = "apple,mistral"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -82,6 +91,9 @@ compatible = "apple,mistral"; reg = <0x0 0x3>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -90,6 +102,9 @@ compatible = "apple,monsoon"; reg = <0x0 0x10004>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_p>; + operating-points-v2 = <&monsoon_opp>; + capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -98,11 +113,107 @@ compatible = "apple,monsoon"; reg = <0x0 0x10005>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_p>; + operating-points-v2 = <&monsoon_opp>; + capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; }; }; + mistral_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <1800>; + }; + opp02 { + opp-hz = /bits/ 64 <453000000>; + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <672000000>; + opp-level = <3>; + clock-latency-ns = <105000>; + }; + opp04 { + opp-hz = /bits/ 64 <972000000>; + opp-level = <4>; + clock-latency-ns = <115000>; + }; + opp05 { + opp-hz = /bits/ 64 <1272000000>; + opp-level = <5>; + clock-latency-ns = <125000>; + }; + opp06 { + opp-hz = /bits/ 64 <1572000000>; + opp-level = <6>; + clock-latency-ns = <135000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp07 { + opp-hz = /bits/ 64 <1680000000>; + opp-level = <7>; + clock-latency-ns = <135000>; + turbo-mode; + }; +#endif + }; + + monsoon_opp: opp-table-1 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <1400>; + }; + opp02 { + opp-hz = /bits/ 64 <453000000>; + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <853000000>; + opp-level = <3>; + clock-latency-ns = <110000>; + }; + opp04 { + opp-hz = /bits/ 64 <1332000000>; + opp-level = <4>; + clock-latency-ns = <110000>; + }; + opp05 { + opp-hz = /bits/ 64 <1812000000>; + opp-level = <5>; + clock-latency-ns = <125000>; + }; + opp06 { + opp-hz = /bits/ 64 <2064000000>; + opp-level = <6>; + clock-latency-ns = <130000>; + }; + opp07 { + opp-hz = /bits/ 64 <2304000000>; + opp-level = <7>; + clock-latency-ns = <140000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <2376000000>; + opp-level = <8>; + clock-latency-ns = <140000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -110,6 +221,18 @@ nonposted-mmio; ranges; + cpufreq_e: performance-controller@208e20000 { + compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x08e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + cpufreq_p: performance-controller@208ea0000 { + compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x08ea0000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@22e600000 { compatible = "apple,s5l-uart"; reg = <0x2 0x2e600000 0x0 0x4000>; @@ -119,6 +242,7 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -127,11 +251,28 @@ reg = <0x2 0x32100000 0x0 0x8000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + pmgr: power-management@232000000 { + compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x32000000 0 0x8c000>; + }; + + dwi_bl: backlight@232200080 { + compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x32200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl_ap: pinctrl@233100000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x33100000 0x0 0x1000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -188,6 +329,14 @@ <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; }; + pmgr_mini: power-management@235200000 { + compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x35200000 0 0x84000>; + }; + wdt: watchdog@2352b0000 { compatible = "apple,t8015-wdt", "apple,wdt"; reg = <0x2 0x352b0000 0x0 0x4000>; @@ -232,3 +381,5 @@ <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; + +#include "t8015-pmgr.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 56b0c67bfcda..2dfe7b895b2b 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -17,6 +17,14 @@ compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M1, 2020)"; + /* + * All of those are used by the bootloader to pass calibration + * blobs and other device-specific properties + */ + aliases { + touchbar0 = &touchbar0; + }; + led-controller { compatible = "pwm-leds"; led-0 { @@ -49,3 +57,53 @@ &fpwm1 { status = "okay"; }; + +&spi0 { + cs-gpios = <&pinctrl_ap 109 GPIO_ACTIVE_LOW>; + status = "okay"; + + touchbar0: touchbar@0 { + compatible = "apple,j293-touchbar"; + reg = <0>; + spi-max-frequency = <11500000>; + spi-cs-setup-delay-ns = <2000>; + spi-cs-hold-delay-ns = <2000>; + reset-gpios = <&pinctrl_ap 139 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 194 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j293.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + touchscreen-inverted-y; + }; +}; + +&display_dfr { + status = "okay"; +}; + +&dfr_mipi_out { + dfr_mipi_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_panel_in>; + }; +}; + +&displaydfr_mipi { + status = "okay"; + + dfr_panel: panel@0 { + compatible = "apple,j293-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; +}; + +&displaydfr_dart { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 5988a4eb6efa..8e82231acab5 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -90,3 +90,5 @@ &nco_clkref { clock-frequency = <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index 9645861a858c..c41c57d63997 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -387,6 +387,15 @@ power-domains = <&ps_sio>, <&ps_spi_p>; }; + ps_spi4: power-controller@260 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + ps_uart_n: power-controller@268 { compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg = <0x268 4>; @@ -558,15 +567,6 @@ apple,always-on; /* Memory controller */ }; - ps_spi4: power-controller@260 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x260 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi4"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - ps_dcs0: power-controller@300 { compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg = <0x300 4>; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 9b0dad6b6184..97b6a067394e 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -326,6 +326,20 @@ clock-output-names = "clkref"; }; + clk_120m: clock-120m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "clk_120m"; + }; + + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -356,6 +370,67 @@ #performance-domain-cells = <0>; }; + display_dfr: display-pipe@228200000 { + compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; + reg = <0x2 0x28200000 0x0 0xc000>, + <0x2 0x28400000 0x0 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + status = "disabled"; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; + + displaydfr_dart: iommu@228304000 { + compatible = "apple,t8103-dart"; + reg = <0x2 0x28304000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 504 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_dispdfr_fe>; + status = "disabled"; + }; + + displaydfr_mipi: dsi@228600000 { + compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x2 0x28600000 0x0 0x100000>; + power-domains = <&ps_mipi_dsi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in_adp: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + dfr_mipi_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + sio_dart: iommu@235004000 { compatible = "apple,t8103-dart"; reg = <0x2 0x35004000 0x0 0x4000>; @@ -441,6 +516,48 @@ status = "disabled"; }; + spi0: spi@235100000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x35100000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@235104000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x35104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 615 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@23510c000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_120m>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -597,6 +714,26 @@ <APPLE_PINMUX(134, 1)>; }; + spi0_pins: spi0-pins { + pinmux = <APPLE_PINMUX(67, 1)>, /* CLK */ + <APPLE_PINMUX(68, 1)>, /* MOSI */ + <APPLE_PINMUX(69, 1)>; /* MISO */ + }; + + spi1_pins: spi1-pins { + pinmux = <APPLE_PINMUX(42, 1)>, + <APPLE_PINMUX(43, 1)>, + <APPLE_PINMUX(44, 1)>, + <APPLE_PINMUX(45, 1)>; + }; + + spi3_pins: spi3-pins { + pinmux = <APPLE_PINMUX(46, 1)>, + <APPLE_PINMUX(47, 1)>, + <APPLE_PINMUX(48, 1)>, + <APPLE_PINMUX(49, 1)>; + }; + pcie_pins: pcie-pins { pinmux = <APPLE_PINMUX(150, 1)>, <APPLE_PINMUX(151, 1)>, diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index 0ad908349f55..3d73f9ee2f46 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -17,8 +17,13 @@ compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M2, 2022)"; + /* + * All of those are used by the bootloader to pass calibration + * blobs and other device-specific properties + */ aliases { bluetooth0 = &bluetooth0; + touchbar0 = &touchbar0; wifi0 = &wifi0; }; @@ -35,6 +40,37 @@ }; }; +&display_dfr { + status = "okay"; +}; + +&dfr_mipi_out { + dfr_mipi_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_panel_in>; + }; +}; + +&displaydfr_mipi { + status = "okay"; + + dfr_panel: panel@0 { + compatible = "apple,j493-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; +}; + +&displaydfr_dart { + status = "okay"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader @@ -67,3 +103,21 @@ &fpwm1 { status = "okay"; }; + +&spi3 { + status = "okay"; + + touchbar0: touchbar@0 { + compatible = "apple,j493-touchbar"; + reg = <0>; + spi-max-frequency = <8000000>; + spi-cs-setup-delay-ns = <2000>; + spi-cs-hold-delay-ns = <2000>; + reset-gpios = <&pinctrl_ap 170 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 174 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j493.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + touchscreen-inverted-y; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi index f5edf61113e7..6da35496a4c8 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -79,3 +79,5 @@ &nco_clkref { clock-frequency = <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 1666e6ab250b..d9b966d68e4f 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -349,6 +349,13 @@ clock-output-names = "clkref"; }; + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -379,6 +386,67 @@ #performance-domain-cells = <0>; }; + display_dfr: display-pipe@228200000 { + compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe"; + reg = <0x2 0x28200000 0x0 0xc000>, + <0x2 0x28400000 0x0 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 618 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + status = "disabled"; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; + + displaydfr_dart: iommu@228304000 { + compatible = "apple,t8110-dart"; + reg = <0x2 0x28304000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_dispdfr_fe>; + status = "disabled"; + }; + + displaydfr_mipi: dsi@228600000 { + compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x2 0x28600000 0x0 0x100000>; + power-domains = <&ps_mipi_dsi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in_adp: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + dfr_mipi_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + sio_dart: iommu@235004000 { compatible = "apple,t8110-dart"; reg = <0x2 0x35004000 0x0 0x4000>; @@ -467,6 +535,34 @@ status = "disabled"; }; + spi1: spi@235104000 { + compatible = "apple,t8112-spi", "apple,spi"; + reg = <0x2 0x35104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 749 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@23510c000 { + compatible = "apple,t8112-spi", "apple,spi"; + reg = <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 751 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkref>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; /* only used in J493 */ + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -626,13 +722,20 @@ <APPLE_PINMUX(130, 1)>; }; - spi3_pins: spi3-pins { + spi1_pins: spi1-pins { pinmux = <APPLE_PINMUX(46, 1)>, <APPLE_PINMUX(47, 1)>, <APPLE_PINMUX(48, 1)>, <APPLE_PINMUX(49, 1)>; }; + spi3_pins: spi3-pins { + pinmux = <APPLE_PINMUX(93, 1)>, + <APPLE_PINMUX(94, 1)>, + <APPLE_PINMUX(95, 1)>, + <APPLE_PINMUX(96, 1)>; + }; + pcie_pins: pcie-pins { pinmux = <APPLE_PINMUX(162, 1)>, <APPLE_PINMUX(163, 1)>, diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index d908e96d7ddc..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index abd013562995..66ba6b027193 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -49,3 +49,29 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index bb9b96fb5314..56ada8728b60 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -29,6 +29,7 @@ device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; }; diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello Fixed Virtual Platform"; + compatible = "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + }; + + net_0: virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + + rng_0: virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + kmi_0: kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts new file mode 100644 index 000000000000..cee49dee7571 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello System Development Platform"; + compatible = "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + clock-output-names = "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dpu_aclk>; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible = "arm,mali-d32", "arm,mali-d71"; + reg = <0x0 0x2cc00000 0x0 0x20000>; + interrupts = <0 69 4>; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells = <1>; + #size-cells = <0>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&dpu_pixel_clk>; + clock-names = "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f000000 0x0 0x40000>; + + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f400000 0x0 0x40000>; + + interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x28 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x4f 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi new file mode 100644 index 000000000000..0bab0b3ea969 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + soc_refclk50mhz: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <85000000>; + clock-output-names = "iofpga:aclk"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,rainier"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_0>; + clocks = <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,rainier"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_1>; + clocks = <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible = "arm,rainier"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_2>; + clocks = <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible = "arm,rainier"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_3>; + clocks = <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent = <&gic>; + + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible = "arm,rainier-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; + + status = "disabled"; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its1: msi-controller@30040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its2: msi-controller@30060000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2ce00000 0x0 0x40000>; + + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "cmdq-sync"; + #iommu-cells = <1>; + }; + + mailbox: mhu@45000000 { + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0x0 0x45000000 0x0 0x1000>; + + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + sram: sram@6000000 { + compatible = "mmio-sram"; + reg = <0x0 0x06000000 0x0 0x8000>; + ranges = <0 0x0 0x06000000 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts index 3a376ab2bb9e..61e064af3337 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts @@ -10,12 +10,17 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/soc/samsung,exynos-usi.h> / { model = "Samsung Galaxy S8 (SM-G950F)"; compatible = "samsung,dreamlte", "samsung,exynos8895"; chassis-type = "handset"; + aliases { + mmc0 = &mmc; + }; + chosen { #address-cells = <2>; #size-cells = <1>; @@ -89,12 +94,60 @@ wakeup-source; }; }; + + /* TODO: Remove once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "reg-placeholder"; + }; +}; + +&hsi2c_23 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + + /* TODO: Update once PMIC is implemented */ + avdd-supply = <®_placeholder>; + vdd-supply = <®_placeholder>; + + interrupt-parent = <&gpa1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int>; + pinctrl-names = "default"; + }; }; &oscclk { clock-frequency = <26000000>; }; +&mmc { + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + + bus-width = <4>; + card-detect-delay = <200>; + cd-gpios = <&gpa1 5 GPIO_ACTIVE_LOW>; + clock-frequency = <800000000>; + disable-wp; + sd-uhs-sdr50; + sd-uhs-sdr104; + + /* TODO: Add regulators once PMIC is implemented */ + + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <1 2>; + samsung,dw-mshc-sdr-timing = <0 3>; + + status = "okay"; +}; + &pinctrl_alive { key_power: key-power-pins { samsung,pins = "gpa2-4"; @@ -123,4 +176,23 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpa1-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; + }; + + ts_int: ts-int-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; + }; +}; + +&usi9 { + samsung,mode = <USI_MODE_I2C0_1>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 36657abfc615..f92d2a8a20a2 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -26,30 +26,6 @@ pinctrl7 = &pinctrl_peric1; }; - arm-a53-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - mongoose-m2-pmu { - compatible = "samsung,mongoose-pmu"; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu4>, - <&cpu5>, - <&cpu6>, - <&cpu7>; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -149,6 +125,30 @@ clock-output-names = "oscclk"; }; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + pmu-mongoose-m2 { + compatible = "samsung,mongoose-pmu"; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + psci { compatible = "arm,psci"; method = "smc"; @@ -228,6 +228,12 @@ "usi1", "usi2", "usi3"; }; + syscon_peric0: syscon@10420000 { + compatible = "samsung,exynos8895-peric0-sysreg", "syscon"; + reg = <0x10420000 0x2000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; + }; + serial_0: serial@10430000 { compatible = "samsung,exynos8895-uart"; reg = <0x10430000 0x100>; @@ -241,6 +247,254 @@ status = "disabled"; }; + usi0: usi@10440000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10440000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1000>; + status = "disabled"; + + hsi2c_5: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart2_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi2_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_6: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1: usi@10460000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10460000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1004>; + status = "disabled"; + + hsi2c_7: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart3_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi3_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_8: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@10480000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10480000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1008>; + status = "disabled"; + + hsi2c_9: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart4_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi4_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_10: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@104a0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x104a0000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x100c>; + status = "disabled"; + + hsi2c_11: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart5_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi5_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_12: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; @@ -273,6 +527,12 @@ "usi10", "usi11", "usi12", "usi13"; }; + syscon_peric1: syscon@10820000 { + compatible = "samsung,exynos8895-peric1-sysreg", "syscon"; + reg = <0x10820000 0x2000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; + }; + serial_1: serial@10830000 { compatible = "samsung,exynos8895-uart"; reg = <0x10830000 0x100>; @@ -286,6 +546,626 @@ status = "disabled"; }; + usi4: usi@10840000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10840000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1008>; + status = "disabled"; + + hsi2c_13: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart6_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_6: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi6_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_14: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@10860000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10860000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x100c>; + status = "disabled"; + + hsi2c_15: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart7_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi7_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_16: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6: usi@10880000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10880000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1010>; + status = "disabled"; + + hsi2c_17: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c17_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart8_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi8_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_18: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7: usi@108a0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108a0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1014>; + status = "disabled"; + + hsi2c_19: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c19_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart9_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi9_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_20: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi8: usi@108c0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108c0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1018>; + status = "disabled"; + + hsi2c_21: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c21_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart10_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi10_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_22: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@108e0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108e0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x101c>; + status = "disabled"; + + hsi2c_23: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c23_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart11_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi11_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_24: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@10900000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10900000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1020>; + status = "disabled"; + + hsi2c_25: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c25_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart12_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_12: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi12_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_26: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@10920000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10920000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1024>; + status = "disabled"; + + hsi2c_27: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c27_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart13_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_13: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi13_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_28: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi12: usi@10940000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10940000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1028>; + status = "disabled"; + + hsi2c_29: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c29_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart14_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_14: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi14_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_30: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi13: usi@10960000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10960000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x102c>; + status = "disabled"; + + hsi2c_31: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c31_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_15: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&uart15_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_15: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi15_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_32: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; + clock-names = "hsi2c"; + interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>; @@ -380,6 +1260,12 @@ "ufs", "usbdrd30"; }; + syscon_fsys0: syscon@11020000 { + compatible = "samsung,exynos8895-fsys0-sysreg", "syscon"; + reg = <0x11020000 0x2000>; + clocks = <&cmu_fsys0 CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK>; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11050000 0x1000>; @@ -398,12 +1284,34 @@ clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + syscon_fsys1: syscon@11420000 { + compatible = "samsung,exynos8895-fsys1-sysreg", "syscon"; + reg = <0x11420000 0x2000>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK>; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11430000 0x1000>; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; }; + mmc: mmc@11500000 { + compatible = "samsung,exynos8895-dw-mshc-smu", + "samsung,exynos7-dw-mshc-smu"; + reg = <0x11500000 0x2000>; + assigned-clocks = <&cmu_top CLK_MOUT_CMU_FSYS1_MMC_CARD>; + assigned-clock-parents = <&cmu_top CLK_FOUT_SHARED4_PLL>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_I_ACLK>, + <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <64>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl_abox: pinctrl@13e60000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x13e60000 0x1000>; diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 9d017dbed952..dd7f99f51a75 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -25,37 +25,6 @@ pinctrl6 = &pinctrl_vts; }; - arm-a55-pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - arm-a76-pmu { - compatible = "arm,cortex-a76-pmu"; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-affinity = <&cpu4>, - <&cpu5>; - }; - - mongoose-m5-pmu { - compatible = "samsung,mongoose-pmu"; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-affinity = <&cpu6>, - <&cpu7>; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -163,6 +132,37 @@ clock-output-names = "oscclk"; }; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-affinity = <&cpu4>, + <&cpu5>; + }; + + pmu-mongoose-m5 { + compatible = "samsung,mongoose-pmu"; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-affinity = <&cpu6>, + <&cpu7>; + }; + psci { compatible = "arm,psci-0.2"; method = "hvc"; @@ -181,6 +181,36 @@ reg = <0x10000000 0x100>; }; + cmu_peris: clock-controller@10020000 { + compatible = "samsung,exynos990-cmu-peris"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names = "oscclk", "bus"; + }; + + timer@10040000 { + compatible = "samsung,exynos990-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>, diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index eb446cdc4ab6..fc6ac531d597 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -89,6 +89,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu1: cpu@100 { @@ -96,6 +103,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu2: cpu@200 { @@ -103,6 +117,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu3: cpu@300 { @@ -110,6 +131,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu4: cpu@10000 { @@ -117,6 +145,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu5: cpu@10100 { @@ -124,6 +159,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu6: cpu@10200 { @@ -131,6 +173,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu7: cpu@10300 { @@ -138,6 +187,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu8: cpu@20000 { @@ -145,6 +201,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x20000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; }; cpu9: cpu@20100 { @@ -152,6 +215,70 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x20100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; + }; + + l2_cache_cl0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl0>; + }; + + l2_cache_cl1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl1>; + }; + + l2_cache_cl2: l2-cache2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl2>; + }; + + l3_cache_cl0: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl1: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl2: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ + cache-line-size = <64>; + cache-sets = <1365>; }; }; @@ -440,6 +567,17 @@ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; }; + ufs_0_phy: phy@16e04000 { + compatible = "samsung,exynosautov920-ufs-phy"; + reg = <0x16e04000 0x4000>; + reg-names = "phy-pma"; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + status = "disabled"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; diff --git a/arch/arm64/boot/dts/exynos/google/Makefile b/arch/arm64/boot/dts/exynos/google/Makefile index 0a6d5e1fe4ee..7385f82b03c9 100644 --- a/arch/arm64/boot/dts/exynos/google/Makefile +++ b/arch/arm64/boot/dts/exynos/google/Makefile @@ -2,3 +2,4 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ gs101-oriole.dtb \ + gs101-raven.dtb diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index e58881c61d53..8df42bedbc03 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -8,273 +8,22 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/usb/pd.h> -#include "gs101-pinctrl.h" -#include "gs101.dtsi" +#include "gs101-pixel-common.dtsi" / { model = "Oriole"; compatible = "google,gs101-oriole", "google,gs101"; - - aliases { - serial0 = &serial_0; - }; - - chosen { - /* Bootloader expects bootargs specified otherwise it crashes */ - bootargs = ""; - stdout-path = &serial_0; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; - pinctrl-names = "default"; - - button-vol-down { - label = "KEY_VOLUMEDOWN"; - linux,code = <KEY_VOLUMEDOWN>; - gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-vol-up { - label = "KEY_VOLUMEUP"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-power { - label = "KEY_POWER"; - linux,code = <KEY_POWER>; - gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - /* TODO: Remove this once PMIC is implemented */ - reg_placeholder: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "placeholder_reg"; - }; - - /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ - ufs_0_fixed_vcc_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "ufs-vcc"; - gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; -}; - -&ext_24_5m { - clock-frequency = <24576000>; -}; - -&ext_200m { - clock-frequency = <200000000>; -}; - -&hsi2c_8 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&hsi2c_12 { - status = "okay"; - /* TODO: add the devices once drivers exist */ - - usb-typec@25 { - compatible = "maxim,max77759-tcpci", "maxim,max33359"; - reg = <0x25>; - interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&typec_int>; - pinctrl-names = "default"; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - self-powered; - try-power-role = "sink"; - op-sink-microwatt = <2600000>; - slow-charger-loop; - /* - * max77759 operating in reverse boost mode (0xA) can - * source up to 1.5A while extboost can only do ~1A. - * Since extboost is the primary path, advertise 900mA. - */ - source-pdos = <PDO_FIXED(5000, 900, - (PDO_FIXED_SUSPEND - | PDO_FIXED_USB_COMM - | PDO_FIXED_DATA_SWAP - | PDO_FIXED_DUAL_ROLE))>; - sink-pdos = <PDO_FIXED(5000, 3000, - (PDO_FIXED_DATA_SWAP - | PDO_FIXED_USB_COMM - | PDO_FIXED_HIGHER_CAP - | PDO_FIXED_DUAL_ROLE)) - PDO_FIXED(9000, 2200, 0) - PDO_PPS_APDO(5000, 11000, 3000)>; - sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, - IDH_PTYPE_DFP_HOST, 2, 0x18d1) - VDO_CERT(0x0) - VDO_PRODUCT(0x4ee1, 0x0) - VDO_UFP(UFP_VDO_VER1_2, - (DEV_USB2_CAPABLE - | DEV_USB3_CAPABLE), - UFP_RECEPTACLE, 0, - AMA_VCONN_NOT_REQ, 0, - UFP_ALTMODE_NOT_SUPP, - UFP_USB32_GEN1) - /* padding */ 0 - VDO_DFP(DFP_VDO_VER1_1, - (HOST_USB2_CAPABLE - | HOST_USB3_CAPABLE), - DFP_RECEPTACLE, 0)>; - sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, - 0, 0, 0x18d1) - VDO_CERT(0x0) - VDO_PRODUCT(0x4ee1, 0x0)>; - /* - * Until bootloader is updated to set those two when - * console is enabled, we disable PD here. - */ - pd-disable; - typec-power-opmode = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdrd31_phy_orien_switch>; - }; - }; - - port@1 { - reg = <1>; - - usbc0_role_sw: endpoint { - remote-endpoint = <&usbdrd31_dwc3_role_switch>; - }; - }; - }; - }; - }; -}; - -&pinctrl_far_alive { - key_voldown: key-voldown-pins { - samsung,pins = "gpa7-3"; - samsung,pin-function = <GS101_PIN_FUNC_EINT>; - samsung,pin-pud = <GS101_PIN_PULL_NONE>; - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; - }; - - key_volup: key-volup-pins { - samsung,pins = "gpa8-1"; - samsung,pin-function = <GS101_PIN_FUNC_EINT>; - samsung,pin-pud = <GS101_PIN_PULL_NONE>; - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; - }; - - typec_int: typec-int-pins { - samsung,pins = "gpa8-2"; - samsung,pin-function = <GS101_PIN_FUNC_EINT>; - samsung,pin-pud = <GS101_PIN_PULL_UP>; - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; - }; -}; - -&pinctrl_gpio_alive { - key_power: key-power-pins { - samsung,pins = "gpa10-1"; - samsung,pin-function = <GS101_PIN_FUNC_EINT>; - samsung,pin-pud = <GS101_PIN_PULL_NONE>; - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&ufs_0 { - status = "okay"; - vcc-supply = <&ufs_0_fixed_vcc_reg>; -}; - -&ufs_0_phy { - status = "okay"; -}; - -&usbdrd31 { - vdd10-supply = <®_placeholder>; - vdd33-supply = <®_placeholder>; - status = "okay"; -}; - -&usbdrd31_dwc3 { - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - maximum-speed = "super-speed-plus"; - status = "okay"; - - port { - usbdrd31_dwc3_role_switch: endpoint { - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbdrd31_phy { - orientation-switch; - /* TODO: Update these once PMIC is implemented */ - pll-supply = <®_placeholder>; - dvdd-usb20-supply = <®_placeholder>; - vddh-usb20-supply = <®_placeholder>; - vdd33-usb20-supply = <®_placeholder>; - vdda-usbdp-supply = <®_placeholder>; - vddh-usbdp-supply = <®_placeholder>; - status = "okay"; - - port { - usbdrd31_phy_orien_switch: endpoint { - remote-endpoint = <&usbc0_orien_sw>; - }; - }; -}; - -&usi_uart { - samsung,clkreq-on; /* needed for UART mode */ - status = "okay"; -}; - -&usi8 { - samsung,mode = <USI_V2_I2C>; - status = "okay"; }; -&usi12 { - samsung,mode = <USI_V2_I2C>; +&cont_splash_mem { + reg = <0x0 0xfac00000 (1080 * 2400 * 4)>; status = "okay"; }; -&watchdog_cl0 { - timeout-sec = <30>; +&framebuffer0 { + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi new file mode 100644 index 000000000000..b25230495c64 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree nodes common for all GS101-based Pixel + * + * Copyright 2021-2023 Google LLC + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/usb/pd.h> +#include "gs101-pinctrl.h" +#include "gs101.dtsi" + +/ { + aliases { + serial0 = &serial_0; + }; + + chosen { + /* Bootloader expects bootargs specified otherwise it crashes */ + bootargs = ""; + stdout-path = &serial_0; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + /* format properties to be added by actual board */ + status = "disabled"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; + pinctrl-names = "default"; + + button-vol-down { + label = "KEY_VOLUMEDOWN"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-vol-up { + label = "KEY_VOLUMEUP"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-power { + label = "KEY_POWER"; + linux,code = <KEY_POWER>; + gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + /* TODO: Remove this once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "placeholder_reg"; + }; + + /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ + ufs_0_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + reserved-memory { + cont_splash_mem: splash@fac00000 { + /* size to be updated by actual board */ + reg = <0x0 0xfac00000 0x0>; + no-map; + status = "disabled"; + }; + }; +}; + +&ext_24_5m { + clock-frequency = <24576000>; +}; + +&ext_200m { + clock-frequency = <200000000>; +}; + +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&hsi2c_12 { + status = "okay"; + /* TODO: add the devices once drivers exist */ + + usb-typec@25 { + compatible = "maxim,max77759-tcpci", "maxim,max33359"; + reg = <0x25>; + interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&typec_int>; + pinctrl-names = "default"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + self-powered; + try-power-role = "sink"; + op-sink-microwatt = <2600000>; + slow-charger-loop; + /* + * max77759 operating in reverse boost mode (0xA) can + * source up to 1.5A while extboost can only do ~1A. + * Since extboost is the primary path, advertise 900mA. + */ + source-pdos = <PDO_FIXED(5000, 900, + (PDO_FIXED_SUSPEND + | PDO_FIXED_USB_COMM + | PDO_FIXED_DATA_SWAP + | PDO_FIXED_DUAL_ROLE))>; + sink-pdos = <PDO_FIXED(5000, 3000, + (PDO_FIXED_DATA_SWAP + | PDO_FIXED_USB_COMM + | PDO_FIXED_HIGHER_CAP + | PDO_FIXED_DUAL_ROLE)) + PDO_FIXED(9000, 2200, 0) + PDO_PPS_APDO(5000, 11000, 3000)>; + sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, + IDH_PTYPE_DFP_HOST, 2, 0x18d1) + VDO_CERT(0x0) + VDO_PRODUCT(0x4ee1, 0x0) + VDO_UFP(UFP_VDO_VER1_2, + (DEV_USB2_CAPABLE + | DEV_USB3_CAPABLE), + UFP_RECEPTACLE, 0, + AMA_VCONN_NOT_REQ, 0, + UFP_ALTMODE_NOT_SUPP, + UFP_USB32_GEN1) + /* padding */ 0 + VDO_DFP(DFP_VDO_VER1_1, + (HOST_USB2_CAPABLE + | HOST_USB3_CAPABLE), + DFP_RECEPTACLE, 0)>; + sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, + 0, 0, 0x18d1) + VDO_CERT(0x0) + VDO_PRODUCT(0x4ee1, 0x0)>; + /* + * Until bootloader is updated to set those two when + * console is enabled, we disable PD here. + */ + pd-disable; + typec-power-opmode = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdrd31_phy_orien_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&usbdrd31_dwc3_role_switch>; + }; + }; + }; + }; + }; +}; + +&pinctrl_far_alive { + key_voldown: key-voldown-pins { + samsung,pins = "gpa7-3"; + samsung,pin-function = <GS101_PIN_FUNC_EINT>; + samsung,pin-pud = <GS101_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + key_volup: key-volup-pins { + samsung,pins = "gpa8-1"; + samsung,pin-function = <GS101_PIN_FUNC_EINT>; + samsung,pin-pud = <GS101_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + typec_int: typec-int-pins { + samsung,pins = "gpa8-2"; + samsung,pin-function = <GS101_PIN_FUNC_EINT>; + samsung,pin-pud = <GS101_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&pinctrl_gpio_alive { + key_power: key-power-pins { + samsung,pins = "gpa10-1"; + samsung,pin-function = <GS101_PIN_FUNC_EINT>; + samsung,pin-pud = <GS101_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&serial_0 { + status = "okay"; +}; + +&ufs_0 { + status = "okay"; + vcc-supply = <&ufs_0_fixed_vcc_reg>; +}; + +&ufs_0_phy { + status = "okay"; +}; + +&usbdrd31 { + vdd10-supply = <®_placeholder>; + vdd33-supply = <®_placeholder>; + status = "okay"; +}; + +&usbdrd31_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + maximum-speed = "super-speed-plus"; + status = "okay"; + + port { + usbdrd31_dwc3_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd31_phy { + orientation-switch; + /* TODO: Update these once PMIC is implemented */ + pll-supply = <®_placeholder>; + dvdd-usb20-supply = <®_placeholder>; + vddh-usb20-supply = <®_placeholder>; + vdd33-usb20-supply = <®_placeholder>; + vdda-usbdp-supply = <®_placeholder>; + vddh-usbdp-supply = <®_placeholder>; + status = "okay"; + + port { + usbdrd31_phy_orien_switch: endpoint { + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&usi8 { + samsung,mode = <USI_V2_I2C>; + status = "okay"; +}; + +&usi12 { + samsung,mode = <USI_V2_I2C>; + status = "okay"; +}; + +&watchdog_cl0 { + timeout-sec = <30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts new file mode 100644 index 000000000000..1e7e6b34b864 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Raven Device Tree + * + * Copyright 2021-2023 Google LLC + * Copyright 2023-2025 Linaro Ltd + */ + +/dts-v1/; + +#include "gs101-pixel-common.dtsi" + +/ { + model = "Raven"; + compatible = "google,gs101-raven", "google,gs101"; +}; + +&cont_splash_mem { + reg = <0x0 0xfac00000 (1440 * 3120 * 4)>; + status = "okay"; +}; + +&framebuffer0 { + width = <1440>; + height = <3120>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index c5335dd59dfe..3de3a758f113 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -73,7 +73,7 @@ compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -83,7 +83,7 @@ compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -103,7 +103,7 @@ compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -113,7 +113,7 @@ compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -123,7 +123,7 @@ compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -133,7 +133,7 @@ compatible = "arm,cortex-x1"; reg = <0x0600>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -143,7 +143,7 @@ compatible = "arm,cortex-x1"; reg = <0x0700>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -151,7 +151,7 @@ idle-states { entry-method = "psci"; - ANANKE_CPU_SLEEP: cpu-ananke-sleep { + ananke_cpu_sleep: cpu-ananke-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -160,7 +160,7 @@ min-residency-us = <2000>; }; - ENYO_CPU_SLEEP: cpu-enyo-sleep { + enyo_cpu_sleep: cpu-enyo-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -169,7 +169,7 @@ min-residency-us = <2500>; }; - HERA_CPU_SLEEP: cpu-hera-sleep { + hera_cpu_sleep: cpu-hera-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -196,6 +196,14 @@ clock-output-names = "ext-200m"; }; + firmware { + acpm_ipc: power-management { + compatible = "google,gs101-acpm-ipc"; + mboxes = <&ap2apm_mailbox>; + shmem = <&apm_sram>; + }; + }; + pmu-0 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; @@ -1400,18 +1408,30 @@ poweroff: syscon-poweroff { compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ - mask = <0x100>; /* reset value */ + mask = <0x00000100>; + value = <0x0>; }; reboot: syscon-reboot { compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ mask = <0x2>; /* SWRESET_SYSTEM */ value = <0x2>; /* reset value */ }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ + mode-bootloader = <0xfc>; + mode-charge = <0x0a>; + mode-fastboot = <0xfa>; + mode-reboot-ab-update = <0x52>; + mode-recovery = <0xff>; + mode-rescue = <0xf9>; + mode-shutdown-thermal = <0x51>; + mode-shutdown-thermal-battery = <0x51>; + }; }; pinctrl_gpio_alive: pinctrl@174d0000 { @@ -1440,6 +1460,15 @@ }; }; + ap2apm_mailbox: mailbox@17610000 { + compatible = "google,gs101-mbox"; + reg = <0x17610000 0x1000>; + clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names = "pclk"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <0>; + }; + pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; @@ -1454,6 +1483,7 @@ /* TODO: update once support for this CMU exists */ clocks = <0>; clock-names = "pclk"; + status = "disabled"; }; cmu_top: clock-controller@1e080000 { @@ -1466,6 +1496,14 @@ }; }; + apm_sram: sram@2039000 { + compatible = "mmio-sram"; + reg = <0x0 0x2039000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2039000 0x40000>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 839432153cc7..b6d3fe26d621 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -122,6 +122,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb + +imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo +imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo +imx8mm-phycore-no-eth-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-eth.dtbo +imx8mm-phycore-no-spiflash-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-spiflash.dtbo +imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-spiflash.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb @@ -193,9 +206,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb @@ -267,6 +283,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb + +imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb @@ -281,6 +301,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index bc0d89427fbe..3a11068f2212 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -87,6 +87,22 @@ los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <2000>; }; + + usb1v2_supply: regulator-usbhub-1v2 { + compatible = "regulator-fixed"; + regulator-name = "usbhub_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + system3v3_supply: regulator-system-3v3 { + compatible = "regulator-fixed"; + regulator-name = "system_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; /* XG1 - Upper SFP */ @@ -231,6 +247,12 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; + + usbhub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; &i2c2 { @@ -378,10 +400,32 @@ }; }; +/* LS1088A USB Port 0 - direct to bottom USB-A port */ &usb0 { status = "okay"; }; +/* LS1088A USB Port 1 - to Microchip USB5744 USB Hub */ &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; + + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index a3fc945aea16..dbea1eefdeec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -790,6 +790,22 @@ status = "okay"; }; +/* Apalis HDMI Audio */ +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, + <722534400>, <45158400>, <11289600>, <49152000>; +}; + /* TODO: Apalis SATA1 */ /* Apalis SPDIF1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 70a8aa1a6791..9b8b1380c4c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -57,8 +57,9 @@ hsio_subsys: bus@5f000000 { ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, @@ -68,9 +69,9 @@ hsio_subsys: bus@5f000000 { bus-range = <0x00 0xff>; device_type = "pci"; interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; @@ -79,6 +80,25 @@ hsio_subsys: bus@5f000000 { status = "disabled"; }; + pcieb_ep: pcie-ep@5f010000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x80000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, + <&pcieb_lpcg IMX_LPCG_CLK_4>, + <&pcieb_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb_lpcg: clock-controller@5f060000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f060000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 6259186cd4d9..5f3b4014e152 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -191,6 +191,33 @@ enable-active-high; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -420,6 +447,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -444,6 +476,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -468,6 +505,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index a8ef4fba16a9..d16490d87687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -254,6 +254,10 @@ status = "okay"; }; +®_nvcc_sd { + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -454,7 +458,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -467,7 +471,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -480,7 +484,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 663ae52b4852..d45542965230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -342,6 +342,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -794,7 +795,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -807,7 +808,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -820,7 +821,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso new file mode 100644 index 000000000000..840f83293452 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include "imx8mm-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + default-brightness-level = <6>; + pwms = <&pwm4 0 50000 0>; + power-supply = <®_vdd_3v3_s>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + brightness-levels= <0 4 8 16 32 64 128 255>; + }; + + panel { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight>; + power-supply = <®_vcc_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_Audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_Analog"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-peb-av-10 { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MM_CLK_SAI5>; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320>; + #sound-dai-cells = <0>; + reg = <0x18>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x57>; + vcc-supply = <®_vdd_3v3_s>; + }; + + eeprom@5f { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x5f>; + size = <32>; + vcc-supply = <®_vdd_3v3_s>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <11289600>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + fsl,sai-mclk-direction-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&iomuxc { + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lcd: lcd0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso new file mode 100644 index 000000000000..a28f51ece93b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Janine Hagemann <j.hagemann@phytec.de> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include "imx8mm-pinfunc.h" + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-0 { + label = "home"; + linux,code = <KEY_HOME>; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = <KEY_MENU>; + gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + + user-led1 { + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x16 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x16 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 5eacbd9611ee..be470cfb03d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -219,9 +219,15 @@ status = "okay"; }; +/* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &snvs_pwrkey { @@ -255,11 +261,12 @@ device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; interrupt-names = "host-wakeup"; interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; max-speed = <2000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt>; shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3>; vddio-supply = <®_vcc_3v3>; }; }; @@ -332,7 +339,7 @@ fsl,pins = < MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x140 >; }; @@ -408,6 +415,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso new file mode 100644 index 000000000000..0fb4b6da6c10 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; +/plugin/; + +ðphy0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso new file mode 100644 index 000000000000..7bfc366c1689 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; +/plugin/; + +&flexspi { + status = "disabled"; +}; + +&som_flash { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso new file mode 100644 index 000000000000..43d5905f3d72 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller <d.haller@phytec.de> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mm-clock.h> + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + core-m4 { + compatible = "fsl,imx8mm-cm4"; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 6069678244f3..672baba4c8d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -69,7 +69,6 @@ /* Ethernet */ &fec1 { - fsl,magic-packet; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; pinctrl-names = "default"; @@ -161,11 +160,13 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; + regulator-min-microvolt = <2500000>; regulator-name = "VCC_ENET_2V5 (LDO3)"; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <2500000>; + regulator-suspend-min-microvolt = <2500000>; }; }; @@ -285,9 +286,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sn65dsi83>; reg = <0x2d>; + vcc-supply = <®_vdd_1v8>; status = "disabled"; }; + /* EEPROM */ eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; @@ -295,17 +298,14 @@ vcc-supply = <®_vdd_3v3_s>; }; + /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; reg = <0x52>; }; }; -/* EMMC */ +/* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; @@ -373,12 +373,6 @@ >; }; - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - pinctrl_sn65dsi83: sn65dsi83grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index c3835b2d860a..755cf9cacd22 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -215,8 +215,13 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &uart1 { @@ -394,6 +399,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tempsense: tempsensegrp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 8f58c84e14c8..b82e9790ea20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index c528594ac442..7251ad3a0017 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -18,20 +18,6 @@ rtc1 = &snvs_rtc; }; - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - /* Fixed clock dedicated to SPI CAN controller */ clk40m: oscillator { compatible = "fixed-clock"; @@ -66,13 +52,6 @@ status = "disabled"; }; - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - status = "disabled"; - }; - /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index c6ad65becc97..475cbf9e0d1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -64,7 +64,6 @@ DVDD-supply = <&buck5_reg>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; ai31xx-micbias-vg = <MICBIAS_AVDDV>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index e68a3fd73e17..640c41b51af9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -63,6 +63,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 68e12a752edd..c26954e5a605 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -74,6 +74,24 @@ clock-frequency = <100000000>; }; + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_audio_pwr: regulator-audio-pwr { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -586,7 +604,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <3 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; }; pca6416: gpio@20 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index e0e9f6f7616d..b97bfeb1c30f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -311,6 +311,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -808,7 +809,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -820,7 +821,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -832,7 +833,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi new file mode 100644 index 000000000000..a1b75c9068b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Pengutronix, Ahmad Fatoum <kernel@pengutronix.de> + */ + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, + <&clk IMX8MP_CLK_A53_CORE>, + <&clk IMX8MP_SYS_PLL3>, + <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_ARM_PLL_OUT>, + <0>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, + <600000000>, + <800000000>, + <600000000>, + <400000000>; + fsl,operating-mode = "nominal"; +}; + +&pgc_hdmimix { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; +}; + +&pgc_hsiomix { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&pgc_gpumix { + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <600000000>, <300000000>; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, <200000000>, + <0>, <0>, <400000000>, + <1039500000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts new file mode 100644 index 000000000000..5a2629f3567c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU basic/fallback"; + compatible = "skov,imx8mp-skov-basic", "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index 33031e946329..020f20c8ce66 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) #include "imx8mp.dtsi" +#include "imx8mp-nominal.dtsi" #include <dt-bindings/leds/common.h> @@ -116,6 +117,11 @@ regulator-name = "24V"; regulator-min-microvolt = <24000000>; regulator-max-microvolt = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg24v>; + interrupts-extended = <&gpio4 23 IRQ_TYPE_EDGE_FALLING>; + system-critical-regulator; + regulator-uv-less-critical-window-ms = <50>; }; reg_can2rs: regulator-can2rs { @@ -163,6 +169,19 @@ }; }; +/* + * Board is passively cooled and heatsink is specced for continuous operation + * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done + * intentionally, not as part of suspend/resume cycles. + */ +&{/opp-table/opp-1600000000} { + /delete-property/ opp-suspend; +}; + +&{/opp-table/opp-1800000000} { + /delete-property/ opp-suspend; +}; + &A53_0 { cpu-supply = <®_vdd_arm>; }; @@ -197,7 +216,7 @@ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-rxid"; status = "okay"; fixed-link { @@ -222,8 +241,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -236,8 +258,8 @@ regulators { reg_vdd_soc: BUCK1 { regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -246,20 +268,20 @@ reg_vdd_arm: BUCK2 { regulator-name = "VDD_ARM"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; + nxp,dvs-run-voltage = <850000>; nxp,dvs-standby-voltage = <850000>; }; reg_vdd_3v3: BUCK4 { regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -267,8 +289,8 @@ reg_vdd_1v8: BUCK5 { regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -276,8 +298,8 @@ reg_nvcc_dram_1v1: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -285,8 +307,8 @@ reg_nvcc_snvs_1v8: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -294,8 +316,8 @@ reg_vdda_1v8: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -313,10 +335,21 @@ }; }; +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + &i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; i2c_rtc: rtc@51 { @@ -331,8 +364,11 @@ &i2c4 { clock-frequency = <380000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; switch: switch@5f { @@ -390,6 +426,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; + /* + * While there is no CTS line, the property "uart-has-rtscts" is still + * the right thing to do to enable the UART to do RS485. In RS485-Mode + * CTS isn't used anyhow and there is no dedicated property + * "uart-has-rts-but-no-cts". + */ + uart-has-rtscts; }; &uart2 { @@ -537,6 +580,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -544,6 +608,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 @@ -551,6 +622,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 @@ -569,6 +647,12 @@ >; }; + pinctrl_reg24v: reg24vgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x154 + >; + }; + pinctrl_reg_vsd_3v3: regvsd3v3grp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 @@ -603,6 +687,8 @@ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 + /* CTS pin is not connected, but needed as workaround */ + MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x140 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts index c1ca69da3cb8..32a429437cbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts @@ -9,12 +9,53 @@ compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp"; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + &iomuxc { pinctrl_hdmi: hdmigrp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 >; }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c2 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts index ccbd3abedd69..baecf768a2ee 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts @@ -8,6 +8,45 @@ model = "SKOV IMX8MP CPU revB - LT6"; compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp"; + lvds-decoder { + compatible = "ti,sn65lvds822", "lvds-decoder"; + power-supply = <®_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + in_lvds1: endpoint { + data-mapping = "vesa-24"; + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l6wh-rt"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_decoder_out>; + }; + }; + }; + touchscreen { compatible = "resistive-adc-touch"; io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; @@ -78,6 +117,27 @@ }; }; +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <462000000>; + status = "okay"; + + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&in_lvds1>; + }; + }; + }; +}; + &pwm1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 2c75da5f064f..45c9a6d55bc9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -27,8 +27,6 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; touchscreen@38 { @@ -51,8 +49,11 @@ }; &lvds_bridge { - /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ - assigned-clock-rates = <490000000>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <980000000>; status = "okay"; ports { @@ -64,18 +65,6 @@ }; }; -&media_blk_ctrl { - /* currently it is not possible to let display clocks confugure - * automatically, so we need to set them manually - */ - assigned-clock-rates = <500000000>, <200000000>, <0>, - /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ - <70000000>, - <500000000>, - /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */ - <490000000>; -}; - &pwm4 { status = "okay"; }; @@ -90,12 +79,3 @@ voltage-table = <3160000 73>; status = "okay"; }; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts new file mode 100644 index 000000000000..b816c6cd3bca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - bd500"; + compatible = "skov,imx8mp-skov-revc-bd500", "fsl,imx8mp"; + + leds { + led_system_red: led-3 { + label = "bd500:system:red"; + color = <LED_COLOR_ID_RED>; + /* Inverted compared to others due to NMOS inverter */ + gpios = <&gpioexp 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_system_green: led-4 { + label = "bd500:system:green"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpioexp 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_lan1_red: led-5 { + label = "bd500:lan1:act"; + color = <LED_COLOR_ID_RED>; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 1 GPIO_ACTIVE_LOW>; + }; + + led_lan1_green: led-6 { + label = "bd500:lan1:link"; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 0 GPIO_ACTIVE_LOW>; + }; + + led_lan2_red: led-7 { + label = "bd500:lan2:act"; + color = <LED_COLOR_ID_RED>; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 6 GPIO_ACTIVE_LOW>; + }; + + led_lan2_green: led-8 { + label = "bd500:lan2:link"; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 7 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-1 { + label = "S1"; + linux,code = <KEY_CONFIG>; + gpios = <&gpioexp 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + gpioexp: gpio@20 { + compatible = "nxp,pca6408"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_exp>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vdd_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl_gpio_exp: gpioexpgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts new file mode 100644 index 000000000000..9a562c011f2c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - TIAN G07017"; + compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp"; + + panel { + compatible = "topland,tian-g07017-01"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + vcc-supply = <®_vdd_3v3>; + iovcc-supply = <®_vdd_3v3>; + wakeup-source; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <358400000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&in_lvds0>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ae64731266f3..23c612e80dd3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -234,7 +234,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "tq-tlv320aic32x"; + model = "tqm-tlv320aic32"; audio-cpu = <&sai3>; audio-codec = <&tlv320aic3x04>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi index 3ddc5aaa7c5f..6067ca3be814 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -41,6 +41,7 @@ spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e0d3b8cba221..ce6793b2d57e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -816,12 +816,12 @@ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, <&clk IMX8MP_CLK_ML_AXI>, <&clk IMX8MP_CLK_ML_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, + assigned-clock-rates = <1000000000>, <800000000>, - <300000000>; + <400000000>; }; pgc_audio: power-domain@5 { @@ -834,7 +834,7 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; assigned-clock-rates = <400000000>, - <600000000>; + <800000000>; }; pgc_gpu2d: power-domain@6 { @@ -1619,10 +1619,11 @@ <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; @@ -2232,9 +2233,9 @@ clock-names = "core", "shader", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>, <1000000000>; power-domains = <&pgc_gpu3d>; }; @@ -2247,8 +2248,8 @@ <&clk IMX8MP_CLK_GPU_AHB>; clock-names = "core", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>; power-domains = <&pgc_gpu2d>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 9d8e7231b7c6..d9f203c79519 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -979,24 +979,27 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index bb37a32ce461..9e0e2d7271ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -794,7 +794,6 @@ interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; - extcon = <&usb3_phy0>; wakeup-source; connector { @@ -1322,25 +1321,28 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; usb-role-switch; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 01e5092e4c40..c92001c80f11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -254,6 +254,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&nvcc_1v8_reg>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi index 81ba8b2831ac..b1c3f331c4ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi @@ -9,8 +9,6 @@ / { model = "Toradex Apalis iMX8QM V1.1"; - compatible = "toradex,apalis-imx8-v1.1", - "fsl,imx8qm"; }; /* TODO: Cooling Maps */ diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index 4d6427fbe875..c18f57039f6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -7,8 +7,6 @@ / { model = "Toradex Apalis iMX8QM"; - compatible = "toradex,apalis-imx8", - "fsl,imx8qm"; }; ðphy0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 50fd3370f7dc..353f825a8ac5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -155,6 +155,13 @@ enable-active-high; }; + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_fec2_supply: regulator-fec2-nvcc { compatible = "regulator-fixed"; regulator-name = "fec2_nvcc"; @@ -220,6 +227,33 @@ regulator-max-microvolt = <1800000>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -244,6 +278,26 @@ }; }; + sound-cs42888 { + compatible = "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -322,12 +376,44 @@ gpio-controller; #gpio-cells = <2>; }; + + cs42888: audio-codec@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cs42888_reset>; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; }; &cm41_intmux { status = "okay"; }; +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + &hsio_phy { fsl,hsio-cfg = "pciea-pcieb-sata"; fsl,refclk-pad-mode = "input"; @@ -439,6 +525,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -718,6 +809,12 @@ >; }; + pinctrl_cs42888_reset: cs42888_resetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + >; + }; + pinctrl_i2c0: i2c0grp { fsl,pins = < IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 @@ -752,6 +849,21 @@ >; }; + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index b1d0189a1725..e80f722dbe65 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -42,6 +42,25 @@ status = "disabled"; }; + pciea_ep: pcie-ep@5f000000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f000000 0x00010000>, + <0x40000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, + <&pciea_lpcg IMX_LPCG_CLK_4>, + <&pciea_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb: pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, @@ -50,8 +69,9 @@ ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso new file mode 100644 index 000000000000..4f562eb5c5b1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include <dt-bindings/phy/phy.h> + +/dts-v1/; +/plugin/; + +&pcieb { + status = "disabled"; +}; + +&pcieb_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index be79c793213a..a669a5d500d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -98,6 +98,33 @@ regulator-name = "cs42888_supply"; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_can_en: regulator-can-en { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -418,6 +445,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; pca6416: gpio@20 { diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index d5abfdb8ede2..ecb35c6b67f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -295,8 +295,8 @@ "", "SODIMM_61", "SODIMM_103", - "", - "", + "SODIMM_79", + "SODIMM_97", "", "SODIMM_25", "SODIMM_27", diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 47c1363a2f99..119a16207059 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -189,6 +189,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + nxp,sd-vsel-fixed-low; }; }; }; @@ -282,6 +283,7 @@ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; }; @@ -553,7 +555,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -565,7 +566,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -577,7 +577,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 8e939d716aac..ebbac5f8d2b2 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; @@ -448,38 +448,38 @@ "WLAN_PERST#", "12V_EN"; /* - * Controls the WiFi card PD pin which is low active - * as power down signal. The output-high states, the signal - * is active, e.g. card is powered down + * Controls the WiFi card's low-active power down pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-pd-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PD#"; }; /* - * Controls the WiFi card disable pin which is low active - * as disable signal. The output-high states, the signal - * is active, e.g. card is disabled + * Controls the WiFi card's low-active disable pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-wdisable-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_W_DISABLE#"; }; /* - * Controls the WiFi card reset pin which is low active - * as reset signal. The output-high states, the signal - * is active, e.g. card in reset + * Controls the WiFi card's reset pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-perst-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PERST#"; }; }; @@ -755,12 +755,6 @@ >; }; - pinctrl_pcf85063: pcf85063grp { - fsl,pins = < - MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 - >; - }; - pinctrl_mipi_csi: mipicsigrp { fsl,pins = < MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ @@ -769,6 +763,12 @@ >; }; + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 + >; + }; + pinctrl_pexp_irq: pexpirqgrp { fsl,pins = < /* HYS | FSEL_0 | No DSE */ @@ -783,17 +783,17 @@ >; }; - pinctrl_temp_sensor_som: tempsensorsomgrp { + pinctrl_tc9595: tc9595-grp { fsl,pins = < - /* HYS | FSEL_0 | no DSE */ - MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 + /* HYS | PD | FSEL_0 | no DSE */ + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 >; }; - pinctrl_tc9595: tc9595-grp { + pinctrl_temp_sensor_som: tempsensorsomgrp { fsl,pins = < - /* HYS | PD | FSEL_0 | no DSE */ - MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 + /* HYS | FSEL_0 | no DSE */ + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 2e953a05c590..9e88c42c3d17 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 56766fdb0b1e..64cd0776b43d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1334,6 +1334,14 @@ #index-cells = <1>; }; + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts new file mode 100644 index 000000000000..514f2429dcbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include <dt-bindings/i3c/i3c.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx95.dtsi" + +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 +#define BRD_SM_CTRL_BT_WAKE 0x8002 +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 +#define BRD_SM_CTRL_BUTTON 0x8004 + +/ { + compatible = "fsl,imx95-15x15-evk", "fsl,imx95"; + model = "NXP i.MX95 15X15 board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + serial0 = &lpuart1; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <64 128 192 255>; + pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-switch1"; + gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vcc_12v: regulator-vcc-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + audio-codec = <&wm8962>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", + "IN3R", "AMIC", "IN1R", "AMIC"; + hp-det-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; + model = "wm8962-audio"; + pinctrl-0 = <&pinctrl_hp>; + pinctrl-names = "default"; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&i3c2 { + i2c-scl-hz = <400000>; + pinctrl-0 = <&pinctrl_i3c2>; + pinctrl-names = "default"; + status = "okay"; + + pca9570: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24 0 (I2C_FILTER)>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "OUT1", "OUT2", "OUT3", "OUT4"; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + >; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_lpi2c6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x00 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 5 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_m2_pwr>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x31e + >; + }; + + pinctrl_i3c2: i3c2grp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40000186 + IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40000186 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_mipi_dsi_csi: mipidsigrp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__SPDIF_IN 0x3fe + IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x3fe + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO08__TPM6_CH0 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>, + <BRD_SM_CTRL_PCIE1_WAKE 1>, + <BRD_SM_CTRL_BT_WAKE 1>, + <BRD_SM_CTRL_PCIE2_WAKE 1>, + <BRD_SM_CTRL_BUTTON 1>; +}; + +&thermal_zones { + a55-thermal { + cooling-maps { + map1 { + cooling-device = <&fan0 0 1>; + trip = <&atrip2>; + }; + + map2 { + cooling-device = <&fan0 1 2>; + trip = <&atrip3>; + }; + + map3 { + cooling-device = <&fan0 2 3>; + trip = <&atrip4>; + }; + }; + + trips { + atrip2: trip2 { + hysteresis = <2000>; + temperature = <55000>; + type = "active"; + }; + + atrip3: trip3 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + + atrip4: trip4 { + hysteresis = <2000>; + temperature = <75000>; + type = "active"; + }; + }; + }; + + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tpm6 { + pinctrl-0 = <&pinctrl_tpm6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&xcvr { + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&dummy>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>, <0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 8bc066c3760c..25ac331f0318 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> #include "imx95.dtsi" #define FALLING_EDGE 1 @@ -317,6 +318,48 @@ interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -418,6 +461,40 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + orientation-switch; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -676,6 +753,12 @@ >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 6b8470cb3461..9bb26b466a06 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -291,6 +291,13 @@ clock-output-names = "sai5_mclk"; }; + clk_sys100m: clock-sys100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_sys100m"; + }; + osc_24m: clock-24m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -673,6 +680,19 @@ status = "disabled"; }; + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C2>, + <&scmi_clk IMX95_CLK_I3C2SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -1245,6 +1265,19 @@ status = "disabled"; }; + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C1>, + <&scmi_clk IMX95_CLK_I3C1SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c1: i2c@44340000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; @@ -1379,6 +1412,7 @@ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk IMX95_CLK_ADC>; clock-names = "ipg"; + #io-channel-cells = <1>; status = "disabled"; }; @@ -1537,6 +1571,56 @@ }; }; + usb3: usb@4c010010 { + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; + reg = <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "hsio", "suspend"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + status = "disabled"; + + usb3_dwc3: usb@4c100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_24M>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "bus_early", "ref", "suspend"; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + iommus = <&smmu 0xe>; + }; + }; + + hsio_blk_ctl: syscon@4c0100c0 { + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; + reg = <0x0 0x4c0100c0 0x0 0x1>; + #clock-cells = <1>; + clocks = <&clk_sys100m>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX95_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + status = "disabled"; + }; + pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x10000>, @@ -1564,8 +1648,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1573,6 +1658,12 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ + msi-map = <0x0 &its 0x10 0x1>, + <0x100 &its 0x11 0x7>; + iommu-map = <0x000 &smmu 0x10 0x1>, + <0x100 &smmu 0x11 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; @@ -1631,8 +1722,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1640,6 +1732,14 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ + msi-map = <0x0 &its 0x98 0x1>, + <0x100 &its 0x99 0x7>; + msi-map-mask = <0x1ff>; + /* smmu have not Devid(BIT[7:6]) */ + iommu-map = <0x000 &smmu 0x18 0x1>, + <0x100 &smmu 0x19 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 58e3865c2889..7ee1228a50f4 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -138,7 +138,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai3>; audio-codec = <&tlv320aic3x04>; }; diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index 276d1683b03b..c4b5663949ad 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -36,6 +36,13 @@ stdout-path = &lpuart1; }; + /* Non-controllable PCIe reference clock generator */ + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -208,6 +215,12 @@ status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c1 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -309,7 +322,15 @@ "", "", "", ""; }; -/* TODO: Mini-PCIe */ +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_1v5>; + status = "okay"; +}; &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, @@ -467,10 +488,10 @@ fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>; }; - pinctrl_pcieb: pcieagrp { - fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, - <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>, - <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; + pinctrl_pcieb: pciebgrp { + fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, + <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000041>, + <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; }; pinctrl_reg_pcie_1v5: regpcie1v5grp { diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 7be430b78c83..ea1456d361a3 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,49 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -333,6 +376,82 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +460,28 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index b9a119eea2b7..c4a195dd67bf 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-evb.dtsi" / { model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)"; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index aaa61a8ad0da..b5ba51696f43 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6c572ffe37ca..991dbfbfa203 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -374,6 +374,51 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -390,6 +435,87 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -398,6 +524,30 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc"; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 828e353455b5..802f543cae4a 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "s32g3.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)"; @@ -39,6 +40,14 @@ status = "okay"; }; +&i2c4 { + current-sensor@40 { + compatible = "ti,ina231"; + reg = <0x40>; + shunt-resistor = <1000>; + }; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi new file mode 100644 index 000000000000..d26af0fb8be7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com> + * Larisa Grigore <larisa.grigore@nxp.com> + */ + +&pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x2c1>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x2b0>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2012>; + }; + }; + + can2_pins: can2-pins { + can2-grp0 { + pinmux = <0x1b2>; + output-enable; + slew-rate = <133>; + }; + + can2-grp1 { + pinmux = <0x1c0>; + input-enable; + slew-rate = <133>; + }; + + can2-grp2 { + pinmux = <0x2782>; + }; + }; + + can3_pins: can3-pins { + can3-grp0 { + pinmux = <0x192>; + output-enable; + slew-rate = <133>; + }; + + can3-grp1 { + pinmux = <0x1a0>; + input-enable; + slew-rate = <133>; + }; + + can3-grp2 { + pinmux = <0x2792>; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x101>, <0x111>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2352>, <0x2362>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x100>, <0x110>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1-grp0 { + pinmux = <0x131>, <0x141>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-grp1 { + pinmux = <0x2cd2>, <0x2ce2>; + }; + }; + + i2c1_gpio_pins: i2c1-gpio-pins { + i2c1-gpio-grp0 { + pinmux = <0x130>, <0x140>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-gpio-grp1 { + pinmux = <0x2cd0>, <0x2ce0>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x2cf0>, <0x2d00>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&can2_pins>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&can3_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi new file mode 100644 index 000000000000..ba53ec622f0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com> + * Larisa Grigore <larisa.grigore@nxp.com> + */ + +&pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x112>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x120>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2013>; + }; + }; + + can1_pins: can1-pins { + can1-grp0 { + pinmux = <0x132>; + output-enable; + slew-rate = <133>; + }; + + can1-grp1 { + pinmux = <0x140>; + input-enable; + slew-rate = <133>; + }; + + can1-grp2 { + pinmux = <0x2772>; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x1f2>, <0x201>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2353>, <0x2363>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x1f0>, <0x200>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x2cf0>, <0x2d00>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; + + pcal6524: gpio-expander@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi index 366912bf3d5e..58693b774d4c 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <66000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; partitions { compatible = "fixed-partitions"; @@ -74,8 +75,6 @@ }; }; -/* TODO GPU */ - &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -114,6 +113,15 @@ }; }; +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + + &mu_m0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index 79a55a0fa2f1..4c6a075908d1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -17,6 +17,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu0>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -34,6 +35,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu1>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -51,6 +53,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu2>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -68,6 +71,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu3>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -160,6 +164,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu4>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -177,6 +182,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu5>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -194,6 +200,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu6>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -211,6 +218,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu7>; + arm,coresight-loses-context-with-cpu; out-ports { port { diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 75377c292bcb..605f5be1538c 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -78,7 +78,7 @@ #size-cells = <2>; ranges; - internal-regs@7f000000 { + bus@7f000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi b/arch/arm64/boot/dts/marvell/armada-371x.dtsi deleted file mode 100644 index dc1182ec9fa1..000000000000 --- a/arch/arm64/boot/dts/marvell/armada-371x.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 371x family of SoCs - * (also named 88F3710) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3710 SoC"; - compatible = "marvell,armada3710", "marvell,armada3700"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 0cfb38492021..bd4e61d5448e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -18,7 +18,7 @@ / { model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; - compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3700"; + compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; chosen { stdout-path = "serial0:115200n8"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts index 6715a19c1483..5c4d8f379704 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; }; &sdhci0 { diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index b3cc2b7b5d19..97a180c8dcd9 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -13,7 +13,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Ultra Board"; compatible = "globalscale,espressobin-ultra", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; aliases { /* ethernet1 is WAN port */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 2a8aa3901a9f..75401eab4d42 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -19,7 +19,7 @@ model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3700"; + "marvell,armada3710"; aliases { /* ethernet1 is wan port */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index b03af87611a9..48a7f50fb427 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board V7"; compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; aliases { /* ethernet1 is wan port */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index c5a834b33b77..1542d836c090 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -16,5 +16,5 @@ / { model = "Globalscale Marvell ESPRESSOBin Board"; - compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3700"; + compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 56930f2ce481..9f4bafeddd82 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -7,7 +7,7 @@ / { model = "GL.iNet GL-MV1000"; - compatible = "glinet,gl-mv1000", "marvell,armada3720"; + compatible = "glinet,gl-mv1000", "marvell,armada3720", "marvell,armada3710"; aliases { led-boot = &led_power; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 54453b0a91f9..f4d73c8b1a6d 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -14,7 +14,7 @@ / { model = "CZ.NIC Turris Mox Board"; compatible = "cznic,turris-mox", "marvell,armada3720", - "marvell,armada3700"; + "marvell,armada3710"; aliases { spi0 = &spi0; diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi index 02ae1e153288..b99ac4c03a48 100644 --- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi @@ -12,9 +12,6 @@ #include "armada-37xx.dtsi" / { - model = "Marvell Armada 3720 SoC"; - compatible = "marvell,armada3720", "marvell,armada3700"; - cpus { cpu1: cpu@1 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 9603223dd761..75b0fdc3efb2 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -11,8 +11,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> / { - model = "Marvell Armada 37xx SoC"; - compatible = "marvell,armada3700"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -78,7 +76,7 @@ #size-cells = <2>; ranges; - internal-regs@d0000000 { + bus@d0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi index 4e46326dd123..570f901b4f4a 100644 --- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi @@ -8,9 +8,3 @@ #include "armada-ap806-dual.dtsi" #include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7020"; - compatible = "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi index 2f440711d21d..710ac44870bd 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-quad.dtsi" #include "armada-70x0.dtsi" -/ { - model = "Marvell Armada 7040"; - compatible = "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi index ba1307c0fadb..b6fc18876093 100644 --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-dual.dtsi" #include "armada-80x0.dtsi" -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock * in CP master is not connected (by package) to the oscillator. So * disable it. However, the RTC clock in CP slave is connected to the diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 225a54ab688d..90ae93274a16 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -371,25 +371,25 @@ }; &cp0_gpio2 { - sata_reset { + sata-reset-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-high; }; - lte_reset { + lte-reset-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-low; }; - wlan_disable { + wlan_disable-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_LOW>; output-low; }; - lte_disable { + lte-disable-hog { gpio-hog; gpios = <21 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index 9c25a88581e4..def25d51c4bf 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -13,7 +13,7 @@ / { model = "IEI-Puzzle-M801"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + compatible = "iei,puzzle-m801", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; aliases { ethernet0 = &cp0_eth0; diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi index 22c2d6ebf381..3efd9b9e6892 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-quad.dtsi" #include "armada-80x0.dtsi" -/ { - model = "Marvell Armada 8040"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi index 299e814d1ded..32bb56f2fe3f 100644 --- a/arch/arm64/boot/dts/marvell/armada-8080.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8080.dtsi @@ -6,9 +6,3 @@ */ #include "armada-ap810-ap0-octa-core.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", - "marvell,armada-ap810"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 3ed6fba1f438..82f4dedfc25e 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -8,9 +8,6 @@ #include "armada-ap806.dtsi" / { - model = "Marvell Armada AP806 Dual"; - compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index cf6a96ddcf40..f37f49c79a50 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -8,9 +8,6 @@ #include "armada-ap806.dtsi" / { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 866628679ac7..73a570cf1010 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -5,14 +5,8 @@ * Device Tree file for Marvell Armada AP806. */ -#define AP_NAME ap806 #include "armada-ap80x.dtsi" -/ { - model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; -}; - &ap_syscon0 { ap_clk: clock { compatible = "marvell,ap806-clock"; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 8848238f9565..e8af7546e893 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -8,9 +8,6 @@ #include "armada-ap807.dtsi" / { - model = "Marvell Armada AP807 Quad"; - compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi index a3328d05fc94..196793d8715c 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi @@ -5,14 +5,8 @@ * Copyright (C) 2019 Marvell Technology Group Ltd. */ -#define AP_NAME ap807 #include "armada-ap80x.dtsi" -/ { - model = "Marvell Armada AP807"; - compatible = "marvell,armada-ap807"; -}; - &ap_syscon0 { ap_clk: clock { compatible = "marvell,ap807-clock"; diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index fdf88cd0eb02..40e146982921 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -48,14 +48,29 @@ }; }; - AP_NAME { + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + + soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; interrupt-parent = <&gic>; ranges; - config-space@f0000000 { + bus@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -122,20 +137,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - odmi: odmi@300000 { compatible = "marvell,odmi-controller"; msi-controller; diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi index d1a7143ef3d4..2e719ffc8289 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi @@ -11,7 +11,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - compatible = "marvell,armada-ap810-octa"; cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi index 2f9ab6b4a2c9..abb37e5fc2c0 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi @@ -10,10 +10,9 @@ /dts-v1/; / { - model = "Marvell Armada AP810"; - compatible = "marvell,armada-ap810"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { serial0 = &uart0_ap0; @@ -25,14 +24,21 @@ method = "smc"; }; - ap810-ap0 { + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; - interrupt-parent = <&gic>; ranges; - config-space@e8000000 { + bus@e8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -62,14 +68,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - xor@400000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x400000 0x1000>, diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 4fd33b0fa56e..e3cfd168becc 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -5,8 +5,4 @@ * Device Tree file for Marvell Armada CP110. */ -#define CP11X_TYPE cp110 - #include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi index 1d0a9653e681..ec6432c8db7c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi @@ -5,8 +5,4 @@ * Device Tree file for Marvell Armada CP115. */ -#define CP11X_TYPE cp115 - #include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 161beec0b6b0..a057e119492f 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -17,7 +17,7 @@ * The contents of the node are defined below, in order to * save one indentation level */ - CP11X_NAME: CP11X_NAME { }; + CP11X_NAME: CP11X_NODE_NAME(bus) { }; /* * CPs only have one sensor in the thermal IC. @@ -51,7 +51,7 @@ interrupt-parent = <&CP11X_LABEL(icu_nsr)>; ranges; - config-space@CP11X_BASE { + bus@CP11X_BASE { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi index cb8d54895a77..a997bbabedd8 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -7,9 +7,6 @@ #include <dt-bindings/gpio/gpio.h> / { - model = "SolidRun CN9130 SoM"; - compatible = "solidrun,cn9130-sr-som", "marvell,cn9130"; - aliases { ethernet0 = &cp0_eth0; ethernet1 = &cp0_eth1; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index b763b73788a4..58484e830063 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -95,13 +95,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb # Device tree overlays support DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ +DTC_FLAGS_mt8395-radxa-nio-12l := -@ diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 150ad84d5d2b..7b10f9c59819 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -15,7 +15,8 @@ #io-channel-cells = <1>; }; - mt6359codec: mt6359codec { + mt6359codec: audio-codec { + compatible = "mediatek,mt6359-codec"; }; regulators { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index b5d4b5baf478..0d995b342d46 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -925,8 +925,6 @@ &pwrap { pmic: pmic { compatible = "mediatek,mt6397"; - #address-cells = <1>; - #size-cells = <1>; interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 3458be7f7f61..6d1d8877b43f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -352,14 +352,14 @@ #clock-cells = <1>; }; - infracfg: power-controller@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - pericfg: power-controller@10003000 { + pericfg: clock-controller@10003000 { compatible = "mediatek,mt8173-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; @@ -564,7 +564,7 @@ memory-region = <&vpu_dma_reserved>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -1255,8 +1255,7 @@ }; pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; + compatible = "mediatek,mt8173-disp-pwm"; reg = <0 0x1401e000 0 0x1000>; #pwm-cells = <2>; clocks = <&mmsys CLK_MM_DISP_PWM026M>, @@ -1266,8 +1265,7 @@ }; pwm1: pwm@1401f000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; + compatible = "mediatek,mt8173-disp-pwm"; reg = <0 0x1401f000 0 0x1000>; #pwm-cells = <2>; clocks = <&mmsys CLK_MM_DISP_PWM126M>, diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts index 3935d83a047e..7bc7c2687d6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -14,16 +14,13 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; + vccio-supply = <&pp1800_alw>; }; &mt6358codec { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index 72852b760038..863f3e403de8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -27,16 +27,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; &qca_wifi { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 757d0afd14fb..e0a583ce4a0b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -14,16 +14,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts index 6641b087e7c5..7874c9a20e12 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -14,16 +14,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index b6abecbcfa81..c5254ae0bb99 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -9,6 +9,7 @@ / { aliases { + dsi0 = &disp_dsi0; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -273,14 +274,27 @@ port { dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; + remote-endpoint = <&dsi0_out>; }; }; }; - port { - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; }; }; }; @@ -296,12 +310,74 @@ pinctrl-0 = <&disp_pwm1_pins>; }; +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + &dp_intf1 { status = "okay"; - port { - dp_intf1_out: endpoint { - remote-endpoint = <&dptx_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dp_intf1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dp_intf1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dptx_in>; + }; }; }; }; @@ -394,6 +470,35 @@ status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_intf1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -513,6 +618,10 @@ }; }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -1029,6 +1138,14 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", @@ -1103,6 +1220,12 @@ }; /* USB detachable base */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + &xhci0 { /* controlled by EC */ vbus-supply = <&pp3300_z1>; @@ -1110,6 +1233,12 @@ }; /* USB3 hub */ +&ssusb1 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + &xhci1 { vusb33-supply = <&pp3300_s3>; vbus-supply = <&pp5000_usb_vbus>; @@ -1117,6 +1246,36 @@ }; /* USB BT */ +&ssusb2 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci2 { /* no power supply since MT7921's power is controlled by PCIe */ /* MT7921's USB BT has issues with USB2 LPM */ diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 338120930b81..69a8423d3858 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,9 +26,11 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; gce1 = &gce1; + merge0 = &merge0; merge1 = &merge1; merge2 = &merge2; merge3 = &merge3; @@ -492,7 +494,7 @@ }; cooling-maps { - map0 { + cpu_little0_cooling_map0: map0 { trip = <&cpu_little0_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -530,7 +532,7 @@ }; cooling-maps { - map0 { + cpu_little1_cooling_map0: map0 { trip = <&cpu_little1_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -568,7 +570,7 @@ }; cooling-maps { - map0 { + cpu_little2_cooling_map0: map0 { trip = <&cpu_little2_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -606,7 +608,7 @@ }; cooling-maps { - map0 { + cpu_little3_cooling_map0: map0 { trip = <&cpu_little3_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -1392,7 +1394,7 @@ compatible = "mediatek,mt8188-afe"; reg = <0 0x10b10000 0 0x10000>; assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; - assigned-clock-parents = <&clk26m>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; clocks = <&clk26m>, <&apmixedsys CLK_APMIXED_APLL1>, <&apmixedsys CLK_APMIXED_APLL2>, @@ -1647,6 +1649,38 @@ status = "disabled"; }; + ssusb1: usb@11201000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + ranges = <0 0 0 0x11200000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, + <&topckgen CLK_TOP_SSUSB_TOP_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x468 2>; + status = "disabled"; + + xhci1: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; + }; + eth: ethernet@11021000 { compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; @@ -1744,27 +1778,6 @@ }; }; - xhci1: usb@11200000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x1000>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port1 PHY_TYPE_USB2>, - <&u3port1 PHY_TYPE_USB3>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, - <&topckgen CLK_TOP_SSUSB_XHCI>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; - clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, - <&topckgen CLK_TOP_SSUSB_TOP_REF>, - <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck"; - mediatek,syscon-wakeup = <&pericfg 0x468 2>; - wakeup-source; - status = "disabled"; - }; - mmc0: mmc@11230000 { compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, @@ -1792,6 +1805,20 @@ status = "disabled"; }; + mmc2: mmc@11250000 { + compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + lvts_mcu: thermal-sensor@11278000 { compatible = "mediatek,mt8188-lvts-mcu"; reg = <0 0x11278000 0 0x1000>; @@ -1851,42 +1878,68 @@ #clock-cells = <1>; }; - xhci2: usb@112a0000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x112a0000 0 0x1000>, - <0 0x112a3e00 0 0x0100>; + ssusb2: usb@112a1000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port2 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>, - <&topckgen CLK_TOP_USB_TOP_3P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112a0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port2 PHY_TYPE_USB2>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x470 2>; status = "disabled"; + + xhci2: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; - xhci0: usb@112b0000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x112b0000 0 0x1000>, - <0 0x112b3e00 0 0x0100>; + ssusb0: usb@112b1000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port0 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>, - <&topckgen CLK_TOP_USB_TOP_2P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112b0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; - mediatek,syscon-wakeup = <&pericfg 0x460 2>; + phys = <&u2port0 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x460 2>; status = "disabled"; + + xhci0: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; pcie: pcie@112f0000 { @@ -2502,6 +2555,23 @@ iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -2512,6 +2582,25 @@ iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -2521,6 +2610,25 @@ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -2530,6 +2638,25 @@ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -2539,6 +2666,25 @@ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -2548,6 +2694,23 @@ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { }; + }; + }; }; dither0: dither@1c007000 { @@ -2557,6 +2720,21 @@ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; disp_dsi0: dsi@1c008000 { @@ -2574,6 +2752,15 @@ status = "disabled"; }; + dsc0: dsc@1c009000 { + compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + disp_dsi1: dsi@1c012000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c012000 0 0x1000>; @@ -2589,6 +2776,17 @@ status = "disabled"; }; + merge0: merge0@1c014000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c015000 0 0x1000>; @@ -2619,6 +2817,21 @@ interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + postmask0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + postmask0_out: endpoint { }; + }; + }; }; vdosys0: syscon@1c01d000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 5056e07399e2..e70599807bb1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -297,12 +297,29 @@ cpu-supply = <&mt6315_6_vbuck1>; }; +&dither0_out { + remote-endpoint = <&dsc0_in>; +}; + &dp_intf0 { status = "okay"; - port { - dp_intf0_out: endpoint { - remote-endpoint = <&edp_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_intf0_in: endpoint { + remote-endpoint = <&merge0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; + }; }; }; }; @@ -310,9 +327,51 @@ &dp_intf1 { status = "okay"; - port { - dp_intf1_out: endpoint { - remote-endpoint = <&dptx_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dp_intf1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dp_intf1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dptx_in>; + }; + }; + }; +}; + +&dsc0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsc0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsc0_out: endpoint { + remote-endpoint = <&merge0_in>; + }; }; }; }; @@ -357,6 +416,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &disp_pwm0 { status = "okay"; @@ -376,8 +464,12 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - dptx_in: endpoint { + + dptx_in: endpoint@1 { + reg = <1>; remote-endpoint = <&dp_intf1_out>; }; }; @@ -511,6 +603,56 @@ }; }; +&merge0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge0_in: endpoint { + remote-endpoint = <&dsc0_out>; + }; + }; + + port@1 { + reg = <1>; + merge0_out: endpoint { + remote-endpoint = <&dp_intf0_in>; + }; + }; + }; +}; + +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_intf1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -612,6 +754,10 @@ }; }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie1 { status = "okay"; @@ -1363,6 +1509,18 @@ status = "okay"; }; +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + /* * For the USB Type-C ports the role and alternate modes switching is * done by the EC so we set dr_mode to host to avoid interfering. @@ -1385,6 +1543,18 @@ status = "okay"; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index f013dbad9dc4..4f2dc0a75566 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3142,6 +3142,23 @@ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -3152,6 +3169,25 @@ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -3161,6 +3197,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -3170,6 +3225,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -3179,6 +3253,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -3188,6 +3281,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@1c007000 { @@ -3197,6 +3309,23 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; dsi0: dsi@1c008000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 44c61094c4d5..1f8584bd66c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -28,6 +28,21 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_connector_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -105,6 +120,16 @@ pinctrl-5 = <&aud_mosi_on_pins>; mediatek,platform = <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vsys_lcm"; + }; + }; &afe { @@ -132,13 +157,102 @@ sram-supply = <&mt6357_vsram_proc_reg>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 = <&dpi_default_pins>; + pinctrl-1 = <&dpi_idle_pins>; + pinctrl-names = "default", "sleep"; + /* + * Ethernet and HDMI (DPI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dpi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dpi0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid015"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + #address-cells = <1>; + #size-cells = <0>; + panel_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dsi0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; phy-handle = <ð_phy>; phy-mode = "rmii"; /* - * Ethernet and HDMI (DSI0) are sharing pins. + * Ethernet and HDMI (DPI0) are sharing pins. * Only one can be enabled at a time and require the physical switch * SW2101 to be set on LAN position * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet @@ -162,6 +276,56 @@ status = "okay"; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-div = <2>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + it66121_hdmi: hdmi@4c { + compatible = "ite,it66121"; + reg = <0x4c>; + #sound-dai-cells = <0>; + interrupt-parent = <&pio>; + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&ite_pins>; + pinctrl-names = "default"; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply = <&mt6357_vsim2_reg>; + vcn33-supply = <&mt6357_vibr_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + it66121_in: endpoint@0 { + reg = <0>; + bus-width = <12>; + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hdmi_connector_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -206,6 +370,11 @@ mediatek,micbias1-microvolt = <1700000>; }; +&mt6357_vsim1_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -268,6 +437,49 @@ }; }; + dpi_default_pins: dpi-default-pins { + pins { + pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>, + <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>, + <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>, + <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>, + <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>, + <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>, + <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>, + <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>, + <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>, + <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>, + <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>, + <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>, + <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>, + <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>, + <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>, + <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>; + drive-strength = <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>, + <MT8365_PIN_1_GPIO1__FUNC_GPIO1>, + <MT8365_PIN_2_GPIO2__FUNC_GPIO2>, + <MT8365_PIN_3_GPIO3__FUNC_GPIO3>, + <MT8365_PIN_4_GPIO4__FUNC_GPIO4>, + <MT8365_PIN_5_GPIO5__FUNC_GPIO5>, + <MT8365_PIN_6_GPIO6__FUNC_GPIO6>, + <MT8365_PIN_7_GPIO7__FUNC_GPIO7>, + <MT8365_PIN_8_GPIO8__FUNC_GPIO8>, + <MT8365_PIN_9_GPIO9__FUNC_GPIO9>, + <MT8365_PIN_10_GPIO10__FUNC_GPIO10>, + <MT8365_PIN_11_GPIO11__FUNC_GPIO11>, + <MT8365_PIN_12_GPIO12__FUNC_GPIO12>, + <MT8365_PIN_13_GPIO13__FUNC_GPIO13>, + <MT8365_PIN_14_GPIO14__FUNC_GPIO14>, + <MT8365_PIN_15_GPIO15__FUNC_GPIO15>; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>; @@ -309,6 +521,33 @@ }; }; + i2c1_pins: i2c1-pins { + pins { + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, + <MT8365_PIN_60_SCL1__FUNC_SCL1_0>; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>, + <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>; + output-high; + }; + + rst_ite_pins { + pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; @@ -464,6 +703,10 @@ status = "okay"; }; +&rdma1_out { + remote-endpoint = <&dpi0_in>; +}; + &ssusb { dr_mode = "otg"; maximum-speed = "high-speed"; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 2bf8c9d02b6e..e6d2b3221a3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/mediatek,mt8365-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/mediatek,mt8365-power.h> @@ -19,6 +20,19 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -609,6 +623,15 @@ status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -705,6 +728,15 @@ status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +764,26 @@ compatible = "mediatek,mt8365-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; smi_common: smi@14002000 { @@ -757,6 +809,290 @@ mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ovl0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ovl0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ccorr0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ccorr0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + aal0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + aal0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + gamma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + gamma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dither0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dither0_out: endpoint@0 { + reg = <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma1_out: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts b/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts new file mode 100644 index 000000000000..71a8cbed1df6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> + */ +/dts-v1/; + +#include "mt8370.dtsi" +#include "mt8390-genio-common.dtsi" + +/ { + model = "MediaTek Genio-510 EVK"; + compatible = "mediatek,mt8370-evk", "mediatek,mt8370", "mediatek,mt8188"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8370.dtsi b/arch/arm64/boot/dts/mediatek/mt8370.dtsi new file mode 100644 index 000000000000..cf1a3759451f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> + */ + +/dts-v1/; +#include "mt8188.dtsi" + +/ { + compatible = "mediatek,mt8370"; + + cpus { + /delete-node/ cpu@400; + /delete-node/ cpu@500; + + cpu-map { + cluster0 { + /delete-node/ core4; + /delete-node/ core5; + }; + }; + }; +}; + +&cpu6 { + clock-frequency = <2200000000>; +}; + +&cpu7 { + clock-frequency = <2200000000>; +}; + +&cpu_little0_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little1_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little2_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little3_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&ppi_cluster0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 04e4a2f73799..612336713a64 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -8,1047 +8,16 @@ /dts-v1/; #include "mt8188.dtsi" -#include "mt6359.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> -#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> -#include <dt-bindings/spmi/spmi.h> -#include <dt-bindings/usb/pd.h> +#include "mt8390-genio-common.dtsi" / { model = "MediaTek Genio-700 EVK"; compatible = "mediatek,mt8390-evk", "mediatek,mt8390", "mediatek,mt8188"; - aliases { - ethernet0 = ð - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - mmc0 = &mmc0; - mmc1 = &mmc1; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0x2 0x00000000>; }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 12 MiB reserved for OP-TEE (BL32) - * +-----------------------+ 0x43e0_0000 - * | SHMEM 2MiB | - * +-----------------------+ 0x43c0_0000 - * | | TA_RAM 8MiB | - * + TZDRAM +--------------+ 0x4340_0000 - * | | TEE_RAM 2MiB | - * +-----------------------+ 0x4320_0000 - */ - optee_reserved: optee@43200000 { - no-map; - reg = <0 0x43200000 0 0x00c00000>; - }; - - scp_mem: memory@50000000 { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - bl31_secmon_reserved: memory@54600000 { - no-map; - reg = <0 0x54600000 0x0 0x200000>; - }; - - apu_mem: memory@55000000 { - compatible = "shared-dma-pool"; - reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ - }; - - vpu_mem: memory@57000000 { - compatible = "shared-dma-pool"; - reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ - }; - - adsp_mem: memory@60000000 { - compatible = "shared-dma-pool"; - reg = <0 0x60000000 0 0xf00000>; - no-map; - }; - - afe_dma_mem: memory@60f00000 { - compatible = "shared-dma-pool"; - reg = <0 0x60f00000 0 0x100000>; - no-map; - }; - - adsp_dma_mem: memory@61000000 { - compatible = "shared-dma-pool"; - reg = <0 0x61000000 0 0x100000>; - no-map; - }; - }; - - common_fixed_5v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - edp_panel_fixed_3v3: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "vedp_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_panel_3v3_en_pins>; - vin-supply = <®_vsys>; - }; - - gpio_fixed_3v3: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "ext_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - /* system wide 4.2V power rail from charger */ - reg_vsys: regulator-vsys { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-always-on; - regulator-boot-on; - }; - - /* used by mmc2 */ - sdio_fixed_1v8: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "vio18_conn"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - }; - - /* used by mmc2 */ - sdio_fixed_3v3: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "wifi_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 74 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - touch0_fixed_3v3: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "vio33_tp1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 119 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_hub_fixed_3v3: regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "vhub_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ - startup-delay-us = <10000>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_p0_vbus: regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "vbus_p0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 84 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_p1_vbus: regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "vbus_p1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 87 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - /* used by ssusb2 */ - usb_p2_vbus: regulator-9 { - compatible = "regulator-fixed"; - regulator-name = "wifi_3v3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; -}; - -&adsp { - memory-region = <&adsp_dma_mem>, <&adsp_mem>; - status = "okay"; -}; - -&afe { - memory-region = <&afe_dma_mem>; - status = "okay"; -}; - -&gpu { - mali-supply = <&mt6359_vproc2_buck_reg>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt9271"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; - irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - AVDD28-supply = <&touch0_fixed_3v3>; - VDDIO-supply = <&mt6359_vio18_ldo_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pins>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <1000000>; - status = "okay"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&mfg0 { - domain-supply = <&mt6359_vproc2_buck_reg>; -}; - -&mfg1 { - domain-supply = <&mt6359_vsram_others_ldo_reg>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_default_pins>; - pinctrl-1 = <&mmc0_uhs_pins>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - supports-cqe; - cap-mmc-hw-reset; - no-sdio; - no-sd; - hs400-ds-delay = <0x1481b>; - vmmc-supply = <&mt6359_vemc_1_ldo_reg>; - vqmmc-supply = <&mt6359_vufs_ldo_reg>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_default_pins>; - pinctrl-1 = <&mmc1_uhs_pins>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - no-mmc; - no-sdio; - cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; - vmmc-supply = <&mt6359_vpa_buck_reg>; - vqmmc-supply = <&mt6359_vsim1_ldo_reg>; -}; - -&mt6359_vbbck_ldo_reg { - regulator-always-on; -}; - -&mt6359_vcn18_ldo_reg { - regulator-name = "vcn18_pmu"; - regulator-always-on; -}; - -&mt6359_vcn33_2_bt_ldo_reg { - regulator-name = "vcn33_2_pmu"; - regulator-always-on; -}; - -&mt6359_vcore_buck_reg { - regulator-name = "dvdd_proc_l"; - regulator-always-on; -}; - -&mt6359_vgpu11_buck_reg { - regulator-name = "dvdd_core"; - regulator-always-on; -}; - -&mt6359_vpa_buck_reg { - regulator-name = "vpa_pmu"; - regulator-max-microvolt = <3100000>; -}; - -&mt6359_vproc2_buck_reg { - /* The name "vgpu" is required by mtk-regulator-coupler */ - regulator-name = "vgpu"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <800000>; - regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; - regulator-coupled-max-spread = <6250>; -}; - -&mt6359_vpu_buck_reg { - regulator-name = "dvdd_adsp"; - regulator-always-on; -}; - -&mt6359_vrf12_ldo_reg { - regulator-name = "va12_abb2_pmu"; - regulator-always-on; -}; - -&mt6359_vsim1_ldo_reg { - regulator-name = "vsim1_pmu"; - regulator-enable-ramp-delay = <480>; -}; - -&mt6359_vsram_others_ldo_reg { - /* The name "vsram_gpu" is required by mtk-regulator-coupler */ - regulator-name = "vsram_gpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <800000>; - regulator-coupled-with = <&mt6359_vproc2_buck_reg>; - regulator-coupled-max-spread = <6250>; -}; - -&mt6359_vufs_ldo_reg { - regulator-name = "vufs18_pmu"; - regulator-always-on; -}; - -&mt6359codec { - mediatek,mic-type-0 = <1>; /* ACC */ - mediatek,mic-type-1 = <3>; /* DCC */ -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins_default>; - status = "okay"; -}; - -&pciephy { - status = "okay"; -}; - -&pio { - audio_default_pins: audio-default-pins { - pins-cmd-dat { - pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>, - <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>, - <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>, - <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>, - <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>, - <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>, - <PINMUX_GPIO107__FUNC_B0_I2SIN_MCK>, - <PINMUX_GPIO108__FUNC_B0_I2SIN_BCK>, - <PINMUX_GPIO109__FUNC_B0_I2SIN_WS>, - <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>, - <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>, - <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>, - <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>, - <PINMUX_GPIO117__FUNC_O_I2SO2_D0>, - <PINMUX_GPIO118__FUNC_O_I2SO2_D1>, - <PINMUX_GPIO121__FUNC_B0_PCM_CLK>, - <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>, - <PINMUX_GPIO124__FUNC_I0_PCM_DI>, - <PINMUX_GPIO125__FUNC_O_DMIC1_CLK>, - <PINMUX_GPIO126__FUNC_I0_DMIC1_DAT>, - <PINMUX_GPIO128__FUNC_O_DMIC2_CLK>, - <PINMUX_GPIO129__FUNC_I0_DMIC2_DAT>; - }; - }; - - dptx_pins: dptx-pins { - pins-cmd-dat { - pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>; - bias-pull-up; - }; - }; - - edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { - pins1 { - pinmux = <PINMUX_GPIO15__FUNC_B_GPIO15>; - output-high; - }; - }; - - eth_default_pins: eth-default-pins { - pins-cc { - pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, - <PINMUX_GPIO140__FUNC_I0_GBE_RXC>, - <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>, - <PINMUX_GPIO142__FUNC_O_GBE_TXEN>; - drive-strength = <8>; - }; - - pins-mdio { - pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, - <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; - drive-strength = <8>; - input-enable; - }; - - pins-power { - pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>, - <PINMUX_GPIO146__FUNC_B_GPIO146>; - output-high; - }; - - pins-rxd { - pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, - <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, - <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, - <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>; - drive-strength = <8>; - }; - - pins-txd { - pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, - <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, - <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, - <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; - drive-strength = <8>; - }; - }; - - eth_sleep_pins: eth-sleep-pins { - pins-cc { - pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, - <PINMUX_GPIO140__FUNC_B_GPIO140>, - <PINMUX_GPIO141__FUNC_B_GPIO141>, - <PINMUX_GPIO142__FUNC_B_GPIO142>; - }; - - pins-mdio { - pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, - <PINMUX_GPIO144__FUNC_B_GPIO144>; - input-disable; - bias-disable; - }; - - pins-rxd { - pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, - <PINMUX_GPIO136__FUNC_B_GPIO136>, - <PINMUX_GPIO137__FUNC_B_GPIO137>, - <PINMUX_GPIO138__FUNC_B_GPIO138>; - }; - - pins-txd { - pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, - <PINMUX_GPIO132__FUNC_B_GPIO132>, - <PINMUX_GPIO133__FUNC_B_GPIO133>, - <PINMUX_GPIO134__FUNC_B_GPIO134>; - }; - }; - - i2c0_pins: i2c0-pins { - pins { - pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, - <PINMUX_GPIO55__FUNC_B1_SCL0>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c1_pins: i2c1-pins { - pins { - pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, - <PINMUX_GPIO57__FUNC_B1_SCL1>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c2_pins: i2c2-pins { - pins { - pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, - <PINMUX_GPIO59__FUNC_B1_SCL2>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c3_pins: i2c3-pins { - pins { - pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, - <PINMUX_GPIO61__FUNC_B1_SCL3>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c4_pins: i2c4-pins { - pins { - pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, - <PINMUX_GPIO63__FUNC_B1_SCL4>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c5_pins: i2c5-pins { - pins { - pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, - <PINMUX_GPIO65__FUNC_B1_SCL5>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - i2c6_pins: i2c6-pins { - pins { - pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, - <PINMUX_GPIO67__FUNC_B1_SCL6>; - bias-pull-up = <MTK_PULL_SET_RSEL_011>; - drive-strength-microamp = <1000>; - }; - }; - - gpio_key_pins: gpio-key-pins { - pins { - pinmux = <PINMUX_GPIO42__FUNC_B1_KPCOL0>, - <PINMUX_GPIO43__FUNC_B1_KPCOL1>, - <PINMUX_GPIO44__FUNC_B1_KPROW0>; - }; - }; - - mmc0_default_pins: mmc0-default-pins { - pins-clk { - pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; - drive-strength = <6>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, - <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, - <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, - <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, - <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, - <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, - <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, - <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, - <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - - pins-rst { - pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - mmc0_uhs_pins: mmc0-uhs-pins { - pins-clk { - pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; - drive-strength = <8>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, - <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, - <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, - <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, - <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, - <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, - <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, - <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, - <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; - input-enable; - drive-strength = <8>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - - pins-ds { - pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; - drive-strength = <8>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-rst { - pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; - drive-strength = <8>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - mmc1_default_pins: mmc1-default-pins { - pins-clk { - pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; - drive-strength = <6>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, - <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, - <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, - <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, - <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - - pins-insert { - pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>; - bias-pull-up; - }; - }; - - mmc1_uhs_pins: mmc1-uhs-pins { - pins-clk { - pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; - drive-strength = <6>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, - <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, - <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, - <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, - <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - mmc2_default_pins: mmc2-default-pins { - pins-clk { - pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; - drive-strength = <4>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, - <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, - <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, - <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, - <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - - pins-pcm { - pinmux = <PINMUX_GPIO123__FUNC_O_PCM_DO>; - }; - }; - - mmc2_uhs_pins: mmc2-uhs-pins { - pins-clk { - pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; - drive-strength = <4>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - - pins-cmd-dat { - pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, - <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, - <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, - <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, - <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - mmc2_eint_pins: mmc2-eint-pins { - pins-dat1 { - pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>; - input-enable; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - mmc2_dat1_pins: mmc2-dat1-pins { - pins-dat1 { - pinmux = <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>; - input-enable; - drive-strength = <6>; - bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - }; - }; - - panel_default_pins: panel-default-pins { - pins-dcdc { - pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>; - output-low; - }; - - pins-en { - pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>; - output-low; - }; - - pins-rst { - pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>; - output-high; - }; - }; - - pcie_pins_default: pcie-default { - mux { - pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, - <PINMUX_GPIO48__FUNC_O_PERSTN>, - <PINMUX_GPIO49__FUNC_B1_CLKREQN>; - bias-pull-up; - }; - }; - - rt1715_int_pins: rt1715-int-pins { - pins_cmd0_dat { - pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; - bias-pull-up; - input-enable; - }; - }; - - spi0_pins: spi0-pins { - pins-spi { - pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, - <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, - <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, - <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; - bias-disable; - }; - }; - - spi1_pins: spi1-pins { - pins-spi { - pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, - <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, - <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, - <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; - bias-disable; - }; - }; - - spi2_pins: spi2-pins { - pins-spi { - pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, - <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, - <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, - <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; - bias-disable; - }; - }; - - touch_pins: touch-pins { - pins-irq { - pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>; - input-enable; - bias-disable; - }; - - pins-reset { - pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>; - output-high; - }; - }; - - uart0_pins: uart0-pins { - pins { - pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, - <PINMUX_GPIO32__FUNC_I1_URXD0>; - bias-pull-up; - }; - }; - - uart1_pins: uart1-pins { - pins { - pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>, - <PINMUX_GPIO34__FUNC_I1_URXD1>; - bias-pull-up; - }; - }; - - uart2_pins: uart2-pins { - pins { - pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, - <PINMUX_GPIO36__FUNC_I1_URXD2>; - bias-pull-up; - }; - }; - - usb_default_pins: usb-default-pins { - pins-iddig { - pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>; - input-enable; - bias-pull-up; - }; - - pins-valid { - pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; - input-enable; - }; - - pins-vbus { - pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>; - output-high; - }; - - }; - - usb1_default_pins: usb1-default-pins { - pins-valid { - pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>; - input-enable; - }; - - pins-usb-hub-3v3-en { - pinmux = <PINMUX_GPIO112__FUNC_B_GPIO112>; - output-high; - }; - }; - - wifi_pwrseq_pins: wifi-pwrseq-pins { - pins-wifi-enable { - pinmux = <PINMUX_GPIO127__FUNC_B_GPIO127>; - output-low; - }; - }; -}; - -ð { - phy-mode ="rgmii-id"; - phy-handle = <ðernet_phy0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ð_default_pins>; - pinctrl-1 = <ð_sleep_pins>; - mediatek,mac-wol; - snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>; - snps,reset-delays-us = <0 10000 10000>; - status = "okay"; -}; - -ð_mdio { - ethernet_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - }; -}; - -&pmic { - interrupt-parent = <&pio>; - interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; - - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power-key { - linux,keycodes = <KEY_POWER>; - wakeup-source; - }; - }; -}; - -&scp { - memory-region = <&scp_mem>; - status = "okay"; -}; - -&sound { - compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; - model = "mt8390-evk"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_default_pins>; - audio-routing = - "Headphone", "Headphone L", - "Headphone", "Headphone R"; - mediatek,adsp = <&adsp>; - status = "okay"; - - dai-link-0 { - link-name = "DL_SRC_BE"; - - codec { - sound-dai = <&pmic 0>; - }; - }; -}; - -&spi2 { - pinctrl-0 = <&spi2_pins>; - pinctrl-names = "default"; - mediatek,pad-select = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; }; -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&u3phy0 { - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; - -&u3phy2 { - status = "okay"; -}; - -&xhci0 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; -}; - -&xhci1 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - #address-cells = <1>; - #size-cells = <0>; - - hub_2_0: hub@1 { - compatible = "usb451,8025"; - reg = <1>; - peer-hub = <&hub_3_0>; - reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&usb_hub_fixed_3v3>; - }; - - hub_3_0: hub@2 { - compatible = "usb451,8027"; - reg = <2>; - peer-hub = <&hub_2_0>; - reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&usb_hub_fixed_3v3>; - }; -}; - -&xhci2 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */ -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi new file mode 100644 index 000000000000..60139e6dffd8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -0,0 +1,1223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Chris Chen <chris-qj.chen@mediatek.com> + * Pablo Sun <pablo.sun@mediatek.com> + * Macpaul Lin <macpaul.lin@mediatek.com> + * + * Copyright (C) 2025 Collabora Ltd. + * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/usb/pd.h> + +/ { + aliases { + ethernet0 = ð + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + dmic_codec: dmic-codec { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <30>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + common_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + edp_panel_fixed_3v3: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vedp_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + vin-supply = <®_vsys>; + }; + + gpio_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "ext_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + /* system wide 4.2V power rail from charger */ + reg_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + /* used by mmc2 */ + sdio_fixed_1v8: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vio18_conn"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + /* used by mmc2 */ + sdio_fixed_3v3: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + touch0_fixed_3v3: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "vio33_tp1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_vreg_pins>; + }; + + usb_hub_fixed_3v3: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "vhub_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ + startup-delay-us = <10000>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + usb_p0_vbus: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + usb_p1_vbus: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + /* used by ssusb2 */ + usb_p2_vbus: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&touch0_fixed_3v3>; + VDDIO-supply = <&mt6359_vio18_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vcn33_1_bt_ldo_reg>; + + port { + it5205_sbu_mux: endpoint { + remote-endpoint = <&typec_sbu_out>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <1000000>; + status = "okay"; + + rt1715@4e { + compatible = "richtek,rt1715"; + reg = <0x4e>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tcpci_int_pins>; + vbus-supply = <&usb_p1_vbus>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + pd-revision = /bits/ 8 <0x03 0x00 0x01 0x08>; + + sink-pdos = <PDO_FIXED(5000, 2000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + source-pdos = <PDO_FIXED(5000, 2000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0x001c1c47>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs1_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&xhci_ss_ep>; + }; + }; + + port@2 { + reg = <2>; + typec_sbu_out: endpoint { + remote-endpoint = <&it5205_sbu_mux>; + }; + + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>, + <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>, + <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>, + <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>, + <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>, + <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>, + <PINMUX_GPIO107__FUNC_B0_I2SIN_MCK>, + <PINMUX_GPIO108__FUNC_B0_I2SIN_BCK>, + <PINMUX_GPIO109__FUNC_B0_I2SIN_WS>, + <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>, + <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>, + <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>, + <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>, + <PINMUX_GPIO117__FUNC_O_I2SO2_D0>, + <PINMUX_GPIO118__FUNC_O_I2SO2_D1>, + <PINMUX_GPIO121__FUNC_B0_PCM_CLK>, + <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>, + <PINMUX_GPIO124__FUNC_I0_PCM_DI>, + <PINMUX_GPIO125__FUNC_O_DMIC1_CLK>, + <PINMUX_GPIO126__FUNC_I0_DMIC1_DAT>, + <PINMUX_GPIO128__FUNC_O_DMIC2_CLK>, + <PINMUX_GPIO129__FUNC_I0_DMIC2_DAT>; + }; + }; + + dptx_pins: dptx-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>; + bias-pull-up; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = <PINMUX_GPIO15__FUNC_B_GPIO15>; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>, + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>, + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; + drive-strength = <8>; + input-enable; + }; + + pins-power { + pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>, + <PINMUX_GPIO146__FUNC_B_GPIO146>; + output-high; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>; + drive-strength = <8>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, + <PINMUX_GPIO140__FUNC_B_GPIO140>, + <PINMUX_GPIO141__FUNC_B_GPIO141>, + <PINMUX_GPIO142__FUNC_B_GPIO142>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, + <PINMUX_GPIO144__FUNC_B_GPIO144>; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, + <PINMUX_GPIO136__FUNC_B_GPIO136>, + <PINMUX_GPIO137__FUNC_B_GPIO137>, + <PINMUX_GPIO138__FUNC_B_GPIO138>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, + <PINMUX_GPIO132__FUNC_B_GPIO132>, + <PINMUX_GPIO133__FUNC_B_GPIO133>, + <PINMUX_GPIO134__FUNC_B_GPIO134>; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, + <PINMUX_GPIO55__FUNC_B1_SCL0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, + <PINMUX_GPIO57__FUNC_B1_SCL1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, + <PINMUX_GPIO59__FUNC_B1_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, + <PINMUX_GPIO61__FUNC_B1_SCL3>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, + <PINMUX_GPIO63__FUNC_B1_SCL4>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, + <PINMUX_GPIO65__FUNC_B1_SCL5>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, + <PINMUX_GPIO67__FUNC_B1_SCL6>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + gpio_key_pins: gpio-key-pins { + pins { + pinmux = <PINMUX_GPIO42__FUNC_B1_KPCOL0>, + <PINMUX_GPIO43__FUNC_B1_KPCOL1>, + <PINMUX_GPIO44__FUNC_B1_KPROW0>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-pcm { + pinmux = <PINMUX_GPIO123__FUNC_O_PCM_DO>; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_dat1_pins: mmc2-dat1-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + panel_default_pins: panel-default-pins { + pins-dcdc { + pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>; + output-low; + }; + + pins-en { + pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>; + output-low; + }; + + pins-rst { + pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>; + output-high; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, + <PINMUX_GPIO48__FUNC_O_PERSTN>, + <PINMUX_GPIO49__FUNC_B1_CLKREQN>; + bias-pull-up; + }; + }; + + rt1715_int_pins: rt1715-int-pins { + pins_cmd0_dat { + pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; + bias-pull-up; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, + <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, + <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, + <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, + <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, + <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, + <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, + <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; + bias-disable; + }; + }; + + touch_vreg_pins: touch-avdd-pins { + pins-power { + pinmux = <PINMUX_GPIO120__FUNC_B_GPIO120>; + output-high; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>; + output-high; + }; + }; + + tcpci_int_pins: tcpci-int-pins { + pins-int-n { + pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, + <PINMUX_GPIO32__FUNC_I1_URXD0>; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>, + <PINMUX_GPIO34__FUNC_I1_URXD1>; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, + <PINMUX_GPIO36__FUNC_I1_URXD2>; + bias-pull-up; + }; + }; + + usb_default_pins: usb-default-pins { + pins-iddig { + pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; + input-enable; + }; + + pins-vbus { + pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>; + output-high; + }; + + }; + + usb1_default_pins: usb1-default-pins { + pins-valid { + pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>; + input-enable; + }; + + pins-usb-hub-3v3-en { + pinmux = <PINMUX_GPIO112__FUNC_B_GPIO112>; + output-high; + }; + }; + + usb2_default_pins: usb2-default-pins { + pins-iddig { + pinmux = <PINMUX_GPIO89__FUNC_B_GPIO89>; + input-enable; + bias-pull-up; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins-wifi-enable { + pinmux = <PINMUX_GPIO127__FUNC_B_GPIO127>; + output-low; + }; + }; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + }; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&sound { + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model = "mt8390-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "DMIC_INPUT", "AP DMIC", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2"; + mediatek,adsp = <&adsp>; + status = "okay"; + + dai-link-0 { + link-name = "DL_SRC_BE"; + + codec { + sound-dai = <&pmic 0>; + }; + }; + + dai-link-1 { + link-name = "DMIC_BE"; + + codec { + sound-dai = <&dmic_codec>; + }; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&ssusb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb_default_pins>; + pinctrl-names = "default"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 83 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_p0_vbus>; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&ssusb1 { + dr_mode = "otg"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb1_default_pins>; + pinctrl-names = "default"; + status = "okay"; + + port { + mtu3_hs1_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8025"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8027"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + port { + xhci_ss_ep: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&ssusb2 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_default_pins>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_p2_vbus>; + }; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 5950194c9ccb..f02c32def593 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -229,6 +229,21 @@ pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + vcc-supply = <&mt6359_vibr_ldo_reg>; + mode-switch; + orientation-switch; + status = "okay"; + + port { + it5205_sbu_ep: endpoint { + remote-endpoint = <&mt6360_ssusb_sbu_ep>; + }; + }; + }; }; &i2c6 { @@ -335,6 +350,63 @@ regulator-always-on; }; }; + + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = <PDO_FIXED(5000, 1000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 2000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + + pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0x00001c46>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&mtu3_ss0_role_sw>; + }; + }; + + port@2 { + reg = <2>; + mt6360_ssusb_sbu_ep: endpoint { + remote-endpoint = <&it5205_sbu_ep>; + }; + }; + }; + }; + }; }; }; @@ -770,6 +842,13 @@ }; }; + u3_p0_vbus: u3-p0-vbus-default-pins { + pins-vbus { + pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; + input-enable; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, @@ -898,8 +977,31 @@ }; &ssusb0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&u3_p0_vbus>; + usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + mtu3_ss0_role_sw: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; }; &ssusb2 { diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso new file mode 100644 index 000000000000..0389c9cb8581 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Radxa Display 8 HD touchscreen module + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +&backlight { + status = "okay"; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_default_pins>; + status = "okay"; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight>; + vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vccio-supply = <&mt6360_ldo2>; + reset-gpios = <&pio 108 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_pins>; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&dsi_panel_in>; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 41dc34837b02..1c922e98441a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -48,6 +48,18 @@ reg = <0 0x40000000 0x1 0x0>; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + enable-gpios = <&pio 107 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <1023>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_pins>; + pwms = <&disp_pwm0 0 500000>; + status = "disabled"; + }; + wifi_vreg: regulator-wifi-3v3-en { compatible = "regulator-fixed"; regulator-name = "wifi_3v3_en"; @@ -172,6 +184,32 @@ cpu-supply = <&mt6315_6_vbuck1>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { }; + }; + }; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -476,6 +514,13 @@ &pio { mediatek,rsel-resistance-in-si-unit; + dsi0_backlight_pins: dsi0-backlight-pins { + pins-backlight-en { + pinmux = <PINMUX_GPIO107__FUNC_GPIO107>; + output-high; + }; + }; + eth_default_pins: eth-default-pins { pins-cc { pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, @@ -673,6 +718,13 @@ }; }; + panel_default_pins: panel-pins { + pins-rst { + pinmux = <PINMUX_GPIO108__FUNC_GPIO108>; + bias-pull-up; + }; + }; + pcie0_default_pins: pcie0-default-pins { pins-bus { pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, @@ -691,6 +743,12 @@ }; }; + pwm0_default_pins: pwm0-pins { + pins-disp-pwm { + pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; + }; + }; + spi1_pins: spi1-default-pins { pins-bus { pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, @@ -711,6 +769,19 @@ }; }; + touch_pins: touch-pins { + pins-touch-int { + pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; + input-enable; + bias-disable; + }; + + pins-touch-rst { + pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; + output-high; + }; + }; + uart0_pins: uart0-pins { pins-bus { pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 1c53ccc5e3cb..9b9d1d15b0c7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -49,6 +49,19 @@ }; }; + i2c@7000c000 { + status = "okay"; + + tmp451: temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 4) IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <&vdd_1v8>; + #thermal-sensor-cells = <1>; + }; + }; + i2c@7000c400 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 63b94a04308e..83ed6ac2a8d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1375,6 +1375,15 @@ #gpio-cells = <2>; gpio-controller; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_FALLING>; + + #interrupt-cells = <2>; + interrupt-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_1v8>; }; exp2: gpio@77 { @@ -1383,6 +1392,15 @@ #gpio-cells = <2>; gpio-controller; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_EDGE_FALLING>; + + #interrupt-cells = <2>; + interrupt-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_1v8>; }; }; @@ -1686,7 +1704,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + gpio = <&exp1 9 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_1v8>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index c56824d7f4d8..0ecdd7243b2e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; regulator-always-on; regulator-boot-on; @@ -281,7 +280,6 @@ regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; regulator-always-on; regulator-boot-on; @@ -296,7 +294,6 @@ regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <350>; regulator-always-on; regulator-boot-on; @@ -311,7 +308,6 @@ regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <360>; regulator-always-on; regulator-boot-on; @@ -326,7 +322,6 @@ regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; regulator-always-on; regulator-boot-on; @@ -341,7 +336,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; maxim,active-fps-power-up-slot = <0>; @@ -354,7 +348,6 @@ regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; maxim,active-fps-power-up-slot = <0>; @@ -371,7 +364,6 @@ regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; regulator-always-on; regulator-boot-on; @@ -395,7 +387,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = <MAX77620_FPS_SRC_1>; maxim,active-fps-power-up-slot = <3>; @@ -408,7 +399,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = <MAX77620_FPS_SRC_1>; maxim,active-fps-power-up-slot = <6>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 942e3a0f81ed..b6c84d195c0e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -874,6 +874,16 @@ pins = "sdmmc3"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; + + gpio_1v8: gpio-1v8 { + pins = "gpio"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + gpio_3v3: gpio-3v3 { + pins = "gpio"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; powergates { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts index 36e888053746..9ce55b4d2de8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -302,6 +302,16 @@ }; pcie@141a0000 { + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ + 0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB) */ + + ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000 /* non-prefetchable memory (128MB) */ + 0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>; /* prefetchable memory (25088MB) */ + status = "okay"; vddio-pex-ctl-supply = <&vdd_1v8_ls>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi index 19340d13f789..41821354bbda 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi @@ -227,13 +227,6 @@ wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_SLEEP>; - }; }; fan: pwm-fan { diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 928635f2e76b..d25e665ee4bf 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo @@ -143,12 +144,16 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo +r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 43f88c199b78..1489bc8d2f4e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -282,6 +282,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 375a56b20f26..a10584150571 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -544,6 +544,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 05712cd96d28..380b857fd273 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -695,6 +695,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ab8283656660..4f38b01ae18d 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -786,6 +786,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 659ae1fed2fa..4e78139d52f6 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -289,6 +289,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f065ee90649a..c8b87aed92a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -215,6 +215,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -222,6 +223,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -262,6 +264,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -400,6 +404,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -480,11 +485,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774a1-rst"; reg = <0 0xe6160000 0 0x018c>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2785,6 +2792,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 117cb6950f91..f2fc2a2035a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -108,6 +108,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -115,6 +116,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -146,6 +148,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -284,6 +288,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -364,11 +369,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774b1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2661,6 +2668,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index b78dbd807d15..57a281fc4977 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -378,6 +378,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 7655d5e3a034..530ffd29cf13 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -103,6 +107,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -134,6 +139,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -257,6 +264,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -337,11 +345,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774c0-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1953,6 +1963,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f845ca604de0..e4dbda8c34d9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -277,6 +277,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -284,6 +285,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -326,6 +328,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -464,6 +468,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -544,11 +549,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774e1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2917,6 +2924,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 96f3b5fe7e92..6ee9cdeb5a3a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -292,6 +292,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -299,6 +300,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -347,6 +349,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -485,6 +488,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -565,11 +569,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7795-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -3398,6 +3404,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ee80f52dc7cf..a323ac47ca70 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7796-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2996,6 +3003,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3b9066043a71..49f6d31c5903 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77961-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2817,6 +2824,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 557bdf8fab17..136a22ca50b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -143,6 +143,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -150,6 +151,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -182,6 +184,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -320,6 +324,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -400,11 +405,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2828,6 +2835,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso index 9450d8ac94cb..0c005660d8dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso @@ -70,7 +70,7 @@ gpio-controller; #gpio-cells = <2>; - vin0_adv7612_en { + vin0-adv7612-en-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-high; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 32f07aa27316..8b594e9e9dc1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -409,6 +409,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 118e77f4477e..445f5dd7c983 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -296,6 +296,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 38145fd6acf0..01744496805c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -67,6 +68,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -91,6 +93,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -200,6 +203,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -280,11 +284,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77970-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1196,6 +1202,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index b409a8d1737e..c2692d6fd00d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -282,6 +282,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 55a6c622f873..f7e506ad7a21 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -80,6 +80,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -87,6 +88,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -120,6 +122,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -229,6 +232,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -309,11 +313,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77980-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1579,6 +1585,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 233af3081e84..6b8742045836 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -118,6 +122,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -149,6 +154,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -272,6 +279,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; i2c_dvfs: i2c@e60b0000 { @@ -368,11 +376,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77990-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2117,6 +2127,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f0828a4675b..b66cd7c90d53 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -65,6 +65,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -86,6 +87,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -209,6 +212,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -289,11 +293,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77995-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1448,6 +1454,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index e8c8fca48b69..0916fd57d1f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -348,6 +348,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index fe6d97859e4a..f1613bfd1632 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -47,6 +47,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -54,6 +55,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a76 { @@ -71,6 +73,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -93,6 +97,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6058180 { @@ -331,11 +336,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779a0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2338,6 +2345,42 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + + fcpvx2: fcp@fedc0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc0000 0 0x200>; + clocks = <&cpg CPG_MOD 1102>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1102>; + iommus = <&ipmmu_vi1 26>; + }; + + fcpvx3: fcp@fedc8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc8000 0 0x200>; + clocks = <&cpg CPG_MOD 1103>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1103>; + iommus = <&ipmmu_vi1 27>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x5000>; @@ -2360,6 +2403,50 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + + vspx2: vsp@fede0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede0000 0 0x8000>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1030>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1030>; + + renesas,fcp = <&fcpvx2>; + }; + + vspx3: vsp@fede8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede8000 0 0x8000>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1031>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1031>; + + renesas,fcp = <&fcpvx3>; + }; + csi40: csi2@feaa0000 { compatible = "renesas,r8a779a0-csi2"; reg = <0 0xfeaa0000 0 0x10000>; @@ -2893,6 +2980,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index e03baefb6a98..1781bb79a619 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi index 5d38669ed1ec..ad2b0398d354 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -5,6 +5,14 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +/ { + aliases { + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; + ethernet2 = &rswitch_port2; + }; +}; + ð_serdes { status = "okay"; }; @@ -42,61 +50,61 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; pinctrl-names = "default"; status = "okay"; +}; + +&rswitch_port0 { + reg = <0>; + phy-handle = <&u101>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + status = "okay"; - ethernet-ports { + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&u101>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u101: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - port@1 { + u101: ethernet-phy@1 { reg = <1>; - phy-handle = <&u201>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u201: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; }; - port@2 { + }; +}; + +&rswitch_port1 { + reg = <1>; + phy-handle = <&u201>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u201: ethernet-phy@2 { reg = <2>; - phy-handle = <&u301>; - phy-mode = "sgmii"; - phys = <ð_serdes 2>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u301: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&rswitch_port2 { + reg = <2>; + phy-handle = <&u301>; + phy-mode = "sgmii"; + phys = <ð_serdes 2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u301: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 054498e54730..b496495c59a6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -253,6 +253,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -260,6 +261,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -296,6 +298,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -315,6 +319,7 @@ compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -463,11 +468,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -974,17 +981,20 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + rswitch_port0: port@0 { reg = <0>; phys = <ð_serdes 0>; + status = "disabled"; }; - port@1 { + rswitch_port1: port@1 { reg = <1>; phys = <ð_serdes 1>; + status = "disabled"; }; - port@2 { + rswitch_port2: port@2 { reg = <2>; phys = <ð_serdes 2>; + status = "disabled"; }; }; }; @@ -1280,6 +1290,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index 5d71d52f9c65..67b18f2bffbd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -22,7 +22,8 @@ i2c5 = &i2c5; serial0 = &hscif0; serial1 = &hscif1; - ethernet0 = &rswitch; + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; }; chosen { @@ -67,6 +68,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; @@ -179,49 +181,42 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; pinctrl-names = "default"; status = "okay"; +}; + +&rswitch_port0 { + reg = <0>; + phy-handle = <&ic99>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + status = "okay"; - ethernet-ports { + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&ic99>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic99: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - - port@1 { + ic99: ethernet-phy@1 { reg = <1>; - phy-handle = <&ic102>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic102: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; }; + }; +}; + +&rswitch_port1 { + reg = <1>; + phy-handle = <&ic102>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; - port@2 { - status = "disabled"; + ic102: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 104f740d20d3..1760720b7128 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -166,6 +166,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -173,6 +174,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -215,6 +217,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -237,6 +241,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, <0 0xe6068000 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -452,11 +457,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779g0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2171,6 +2178,24 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x7000>; @@ -2193,6 +2218,28 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779g0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2453,49 +2500,10 @@ }; }; - fcpvx0: fcp@fedb0000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb0000 0 0x200>; - clocks = <&cpg CPG_MOD 1100>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1100>; - iommus = <&ipmmu_vi1 24>; - }; - - fcpvx1: fcp@fedb8000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb8000 0 0x200>; - clocks = <&cpg CPG_MOD 1101>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1101>; - iommus = <&ipmmu_vi1 25>; - }; - - vspx0: vsp@fedd0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd0000 0 0x8000>; - interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1028>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1028>; - - renesas,fcp = <&fcpvx0>; - }; - - vspx1: vsp@fedd8000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd8000 0 0x8000>; - interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 1029>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1029>; - - renesas,fcp = <&fcpvx1>; - }; - prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 18fd52f55de5..4d890e0617af 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -46,6 +46,8 @@ serial0 = &hscif0; serial1 = &hscif2; ethernet0 = &avb0; + ethernet1 = &avb1; + ethernet2 = &avb2; }; can_transceiver0: can-phy0 { @@ -200,17 +202,64 @@ &avb0 { pinctrl-0 = <&avb0_pins>; pinctrl-names = "default"; - phy-handle = <&phy0>; + phy-handle = <&avb0_phy>; tx-internal-delay-ps = <2000>; status = "okay"; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>; + }; }; }; @@ -233,25 +282,6 @@ }; }; -&dsi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - &csi40 { status = "okay"; @@ -292,6 +322,25 @@ }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -312,6 +361,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; @@ -558,6 +608,56 @@ }; }; + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + can_clk_pins: can-clk { groups = "can_clk"; function = "can_clk"; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index d0c01c0fdda2..8524a1e7205e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -138,6 +138,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr-clk { @@ -145,6 +146,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -180,6 +182,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -201,6 +205,7 @@ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -401,11 +406,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -793,8 +800,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -842,8 +847,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -891,8 +894,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 2>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1908,6 +1909,15 @@ resets = <&cpg 508>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; @@ -1918,6 +1928,17 @@ renesas,fcp = <&fcpvd0>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779h0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2144,6 +2165,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts new file mode 100644 index 000000000000..3267e7b75b58 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the MYIR Remi Pi + * + * Copyright (C) 2022 MYIR Electronics Corp. + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#include "r9a07g044l2.dtsi" + +/ { + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + + mmc0 = &sdhi0; + + serial0 = &scif0; + serial4 = &scif4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c1>; + + port { + hdmi_con: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + remote-endpoint = <<8912_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&gpu { + mali-supply = <®_1p1v>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + clock-frequency = <400000>; + status = "okay"; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8912_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&mtu3 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ + <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */ + <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */ + <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; + + scif4_pins: scif4 { + pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */ + <RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */ + }; + + sdhi0_pins: sd0 { + sd0-ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0-data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0-rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a9b98db9ef95..0364f89776e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -28,6 +28,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-137500000 { + opp-hz = /bits/ 64 <137500000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -40,6 +67,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -443,7 +471,6 @@ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; - status = "disabled"; }; pinctrl: pinctrl@11030000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso new file mode 100644 index 000000000000..4a81e3a3c8bd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC Carrier II EVK + * +--------------------------------------------+ + * |PMOD1_3A (PMOD1 PIN HEADER) | + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | + * | GND (pin5) (pin11) GND | + * | PWR_PMOD1 (pin6) (pin12) GND | + * +--------------------------------------------+ + * + * The following switches should be set as follows for SCIF1: + * - SW_CONFIG2: ON + * - SW_OPT_MUX4: ON + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> +#include "rzg3s-smarc-switches.h" + +&pinctrl { + scif1_pins: scif1-pins { + pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */ + <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */ + <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */ + <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS# */ + }; +}; + +#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON +&scif1 { + pinctrl-names = "default"; + pinctrl-0 = <&scif1_pins>; + uart-has-rtscts; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 200e9ea89193..c93aa16d0a6e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -154,6 +154,13 @@ #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; @@ -175,6 +182,36 @@ status = "disabled"; }; + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1c550b22b164..0cd00bb05191 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -105,6 +105,35 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + opp-microvolt = <800000>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-microvolt = <800000>; + }; + + opp-157500000 { + opp-hz = /bits/ 64 <157500000>; + opp-microvolt = <800000>; + }; + + opp-78750000 { + opp-hz = /bits/ 64 <78750000>; + opp-microvolt = <800000>; + }; + + opp-19687500 { + opp-hz = /bits/ 64 <19687500>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -249,7 +278,6 @@ reg = <0 0x10430000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; resets = <&cpg 0x30>; - status = "disabled"; }; ostm0: timer@11800000 { @@ -582,6 +610,28 @@ status = "disabled"; }; + gpu: gpu@14850000 { + compatible = "renesas,r9a09g057-mali", + "arm,mali-bifrost"; + reg = <0x0 0x14850000 0x0 0x10000>; + interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD 0xf0>, + <&cpg CPG_MOD 0xf1>, + <&cpg CPG_MOD 0xf2>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg 0xdd>, + <&cpg 0xde>, + <&cpg 0xdf>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + }; + gic: interrupt-controller@14900000 { compatible = "arm,gic-v3"; reg = <0x0 0x14900000 0 0x20000>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 0b705c987b6c..063eca0ba3e2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -43,6 +43,16 @@ reg = <0x2 0x40000000 0x2 0x00000000>; }; + reg_0p8v: regulator0 { + compatible = "regulator-fixed"; + + regulator-name = "fixed-0.8V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator1 { compatible = "regulator-fixed"; @@ -68,6 +78,11 @@ clock-frequency = <22579200>; }; +&gpu { + status = "okay"; + mali-supply = <®_0p8v>; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts new file mode 100644 index 000000000000..d2586d278769 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for Yuridenki-Shokai the Kakip board + * + * Copyright (C) 2024 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + */ + +/dts-v1/; + +#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> +#include <dt-bindings/gpio/gpio.h> +#include "r9a09g057.dtsi" + +/ { + model = "Yuridenki-Shokai Kakip Board based on r9a09g057h48"; + compatible = "yuridenki,kakip", "renesas,r9a09g057h48", "renesas,r9a09g057"; + + aliases { + serial0 = &scif; + mmc0 = &sdhi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xF8000000>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + gpios = <&pinctrl RZV2H_GPIO(A, 0) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_RXD", "SCIF_TXD"; + }; + + sd0-pwr-en-hog { + gpio-hog; + gpios = <RZV2H_GPIO(A, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sd0_pwr_en"; + }; + + sdhi0_pins: sd0 { + sd0-clk { + pins = "SD0CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-mux { + pinmux = <RZV2H_PORT_PINMUX(A, 5, 15)>; /* SD0_CD */ + }; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <4>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 6b583ae2ac52..f4ba050beb0d 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -26,3 +26,7 @@ &rtxin_clk { clock-frequency = <32768>; }; + +&wdt1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..39845faec894 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,25 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* - * On-board switches' states: - * @SW_OFF: switch's state is OFF - * @SW_ON: switch's state is ON - */ -#define SW_OFF 0 -#define SW_ON 1 - -/* - * SW_CONFIG[x] switches' states: - * @SW_CONFIG2: - * SW_OFF - SD0 is connected to eMMC - * SW_ON - SD0 is connected to uSD0 card - * @SW_CONFIG3: - * SW_OFF - SD2 is connected to SoC - * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - */ -#define SW_CONFIG2 SW_OFF -#define SW_CONFIG3 SW_ON +#include "rzg3s-smarc-switches.h" / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h new file mode 100644 index 000000000000..bbf908a5322c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II + * boards. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RZG3S_SMARC_SWITCHES_H__ +#define __RZG3S_SMARC_SWITCHES_H__ + +/* + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON + */ +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_OFF +#define SW_CONFIG3 SW_ON + +/* + * SW_OPT_MUX[x] switches' states: + * @SW_OPT_MUX4: + * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART + * SW_ON - The SMARC SER0 signals are routed to PMOD1 + */ +#define SW_OPT_MUX4 SW_ON + +#endif /* __RZG3S_SMARC_SWITCHES_H__ */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 81b4ffd1417d..5e044a4d0234 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,8 @@ / { aliases { i2c0 = &i2c0; + serial0 = &scif1; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +164,11 @@ <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ }; + scif3_pins: scif3 { + pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */ + <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +215,12 @@ status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 06c7e9746304..68971c870d17 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -940,6 +940,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi index 8ae6af1af094..4caa0281a687 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -35,13 +39,18 @@ routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; dais = <&snd_kf1 /* (C) CPU2 */ &snd_kf2 /* (D) CPU3 */ &snd_kf3 /* (E) CPU4 */ &snd_kf4 /* (F) CPU5 */ - &snd_kf5 /* (G) GPU6 */ + &snd_kf5 /* (G) CPU6 */ + &snd_kf6 /* (H) CPU7 */ + &snd_kf7 /* (I) CPU8 */ >; }; }; @@ -50,7 +59,9 @@ ports { #address-cells = <1>; #size-cells = <0>; + mclk-fs = <512>; + prefix = "pcm3168a"; /* * (Y) PCM3168A-p @@ -59,7 +70,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - prefix = "pcm3168a"; convert-channels = <8>; /* to 8ch TDM */ /* (C) CPU2 -> (Y) PCM3168A-p */ @@ -91,10 +101,28 @@ * (Z) PCM3168A-c */ port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + convert-channels = <6>; /* to 6ch TDM */ + /* (G) CPU6 <- PCM3168A-c */ - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; + pcm3168a_endpoint_c1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_pcm3168a_capture1>; + clocks = <&clksndsel>; + }; + /* (H) CPU7 <- PCM3168A-c */ + pcm3168a_endpoint_c2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_pcm3168a_capture2>; + clocks = <&clksndsel>; + }; + /* (I) CPU8 <- PCM3168A-c */ + pcm3168a_endpoint_c3: endpoint@2 { + reg = <2>; + remote-endpoint = <&rsnd_for_pcm3168a_capture3>; clocks = <&clksndsel>; }; }; @@ -160,12 +188,35 @@ */ snd_kf5: port@6 { reg = <6>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; + rsnd_for_pcm3168a_capture1: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c1>; + bitclock-master; + frame-master; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + snd_kf6: port@7 { + reg = <7>; + rsnd_for_pcm3168a_capture2: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c2>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + snd_kf7: port@8 { + reg = <8>; + rsnd_for_pcm3168a_capture3: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c3>; bitclock-master; frame-master; - dai-tdm-slot-num = <6>; - capture = <&ssi4>; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi index 4cf632bc4621..67a0057a3383 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -36,19 +40,25 @@ "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", "pcm3168a Playback", "DAI5 Playback", - "DAI6 Capture", "pcm3168a Capture"; + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; links = <&fe_c /* (C) CPU2 */ &fe_d /* (D) CPU3 */ &fe_e /* (E) CPU4 */ &fe_f /* (F) CPU5 */ - &rsnd_g /* (G) CPU6 */ + &fe_g /* (G) CPU6 */ + &fe_h /* (H) CPU7 */ + &fe_i /* (I) CPU8 */ &be_y /* (Y) PCM3168A-p */ + &be_z /* (Z) PCM3168A-c */ >; - dpcm { + dpcm: dpcm { #address-cells = <1>; #size-cells = <0>; + non-supplier; ports@0 { #address-cells = <1>; @@ -62,21 +72,32 @@ * (D) CPU3 * (E) CPU4 * (F) CPU5 + * (G) CPU6 + * (H) CPU7 + * (I) CPU8 */ fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + + fe_g: port@6 { reg = <6>; fe_g_ep: endpoint { remote-endpoint = <&rsnd_g_ep>; }; }; + fe_h: port@7 { reg = <7>; fe_h_ep: endpoint { remote-endpoint = <&rsnd_h_ep>; }; }; + fe_i: port@8 { reg = <8>; fe_i_ep: endpoint { remote-endpoint = <&rsnd_i_ep>; }; }; }; ports@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; /* * BE * * (Y) PCM3168A-p + * (Z) PCM3168A-c */ - be_y: port { be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_y: port@0 { reg = <0>; be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_z: port@1 { reg = <1>; be_z_ep: endpoint { remote-endpoint = <&pcm3168a_z_ep>; }; }; }; }; }; @@ -106,8 +127,9 @@ */ port@1 { reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ pcm3168a_z_ep: endpoint { - remote-endpoint = <&rsnd_g_ep>; + remote-endpoint = <&be_z_ep>; clocks = <&clksndsel>; }; }; @@ -171,13 +193,37 @@ /* * (G) CPU6 */ - rsnd_g: port@6 { + port@6 { reg = <6>; rsnd_g_ep: endpoint { - remote-endpoint = <&pcm3168a_z_ep>; + remote-endpoint = <&fe_g_ep>; + bitclock-master; + frame-master; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + port@7 { + reg = <7>; + rsnd_h_ep: endpoint { + remote-endpoint = <&fe_h_ep>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + port@8 { + reg = <8>; + rsnd_i_ep: endpoint { + remote-endpoint = <&fe_i_ep>; bitclock-master; frame-master; - capture = <&ssi4>; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi index f01d91aaadf3..fd75801c329e 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { @@ -39,7 +43,10 @@ simple-audio-card,routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; simple-audio-card,dai-link@0 { #address-cells = <1>; @@ -88,16 +95,40 @@ }; simple-audio-card,dai-link@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ + /* * (G) CPU6 */ - cpu { + cpu@0 { + reg = <0>; bitclock-master; frame-master; sound-dai = <&rcar_sound 6>; }; /* + * (H) CPU7 + */ + cpu@1 { + reg = <1>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 7>; + }; + /* + * (I) CPU8 + */ + cpu@2 { + reg = <2>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 8>; + }; + + /* * (Z) PCM3168A-c */ codec { @@ -151,7 +182,19 @@ * (G) CPU6 */ dai6 { - capture = <&ssi4>; + capture = <&ssiu40 &ssi4>; + }; + /* + * (H) CPU7 + */ + dai7 { + capture = <&ssiu41 &ssi4>; + }; + /* + * (I) CPU8 + */ + dai8 { + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0c58d816c375..fcab957b54f7 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -448,6 +448,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index f24814d7c924..b4024e85ae5a 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -201,6 +201,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi index 9017c4475a7c..a5d1c1008e7e 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi @@ -21,7 +21,9 @@ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = <MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC + MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA + MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC>; remote-endpoint = <&max96712_out0>; }; }; @@ -42,7 +44,9 @@ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = <MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC + MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA + MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC>; remote-endpoint = <&max96712_out1>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index def1222c1907..3e8771ef69ba 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-firefly-jd4-core-mb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-lvds-9904379.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-bpi-p2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb @@ -61,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb @@ -122,6 +125,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb @@ -132,6 +136,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb @@ -145,11 +151,14 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-ultra.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb @@ -170,3 +179,57 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb + +# Overlay application tests +# +# A .dtbo must have its own +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay>.dtbo +# +# entry, and at least one overlay application test reflecting a possible +# hardware combination in real life: +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) += <overlay-application-test>.dtb +# <overlay-application-test>-dtbs := <base>.dtb <overlay-1>.dtbo [<overlay-2>.dtbo ...] +# +# This will make the <base>.dtb have symbols (like when DTC_FLAGS has -@ passed) +# and generate a new DTB (<overlay-application-test>.dtb) which is the +# result of the application of <overlay-1>.dtbo and other listed overlays on top +# of <base>.dtb. + +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-lvds-9904379.dtb +px30-ringneck-haikou-haikou-lvds-9904379-dtbs := px30-ringneck-haikou.dtb \ + px30-ringneck-haikou-lvds-9904379.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb +px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \ + px30-ringneck-haikou-video-demo.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-haikou-video-demo.dtb +rk3399-puma-haikou-haikou-video-demo-dtbs := rk3399-puma-haikou.dtb \ + rk3399-puma-haikou-video-demo.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb +rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \ + rk3568-wolfvision-pf5-display-vz.dtbo \ + rk3568-wolfvision-pf5-io-expander.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb +rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-wifi.dtb +rk3588-edgeble-neu6b-wifi-dtbs := rk3588-edgeble-neu6b-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtb +rk3588-jaguar-pre-ict-tester-dtbs := rk3588-jaguar.dtb \ + rk3588-jaguar-pre-ict-tester.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtb +rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-ep.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb +rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-srns.dtbo diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso new file mode 100644 index 000000000000..3fc088a5636a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-lvds-9904379.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard. + * + * This adapter needs to be plugged in the fake PCIe connector called Video + * Connector on Haikou carrierboard. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + brightness-levels = <0 255>; + default-brightness-level = <255>; + num-interpolated-steps = <255>; + power-supply = <&vcc3v3_baseboard>; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "admatec,9904379", "panel-lvds"; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + height-mm = <126>; + power-supply = <&vcc3v3_baseboard>; + width-mm = <224>; + + panel-timing { + clock-frequency = <49500000>; + hactive = <1024>; + hback-porch = <90>; + hfront-porch = <90>; + hsync-len = <90>; + vactive = <600>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <10>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* EEPROM and GT928 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int &touch_rst>; + pinctrl-names = "default"; + touchscreen-inverted-x; + touchscreen-inverted-y; + AVDD28-supply = <&vcc3v3_baseboard>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + eeprom@54 { + reg = <0x54>; + compatible = "st,24c04", "atmel,24c04"; + pagesize = <16>; + size = <512>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&lvds { + status = "okay"; +}; + +&lvds_out { + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso new file mode 100644 index 000000000000..7d9ea5aa5984 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Ringneck system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/px30-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index 1a59e8b1dc46..91cf4cd3fae2 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -154,6 +154,8 @@ }; &i2c3 { + status = "okay"; + eeprom@50 { reg = <0x50>; compatible = "atmel,24c01"; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index e80412abec08..142244d52706 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -325,10 +325,6 @@ }; }; -&i2c3 { - status = "okay"; -}; - &i2s0_8ch { rockchip,trcm-sync-tx-only; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 629121de5a13..5e7181948992 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -147,7 +147,7 @@ &pwm5 { status = "okay"; - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm5_pin_pull_down>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts index a94114fb7cc1..96c27fc5005d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts @@ -274,13 +274,13 @@ &pwm0 { pinctrl-0 = <&pwm0_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; &pwm1 { pinctrl-0 = <&pwm1_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts index 6310b58de77f..a4bdd87d0729 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -428,10 +428,18 @@ status = "okay"; }; +&u2phy_otg { + status = "okay"; +}; + &uart2 { status = "okay"; }; +&usb20_otg { + status = "okay"; +}; + &usbdrd3 { dr_mode = "host"; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index b169be06d4d1..c8eb5481f43d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -603,7 +603,7 @@ }; &pwm2 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin_pull_down>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso new file mode 100644 index 000000000000..0377ec860d35 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 947bbd62a6b0..f2234dabd664 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -149,8 +149,15 @@ }; }; +&gmac { + status = "okay"; +}; + &hdmi { - ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { status = "okay"; }; @@ -186,9 +193,22 @@ }; }; -&i2c6 { +&i2c7 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { status = "okay"; - clock-frequency = <400000>; }; &pcie_phy { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 995b30a7aae0..e00fbaa8acc1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -183,7 +183,6 @@ snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x23>; - status = "okay"; }; &gpu { @@ -389,6 +388,14 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; +}; + +&i2c6 { + clock-frequency = <400000>; +}; + &i2c7 { status = "okay"; clock-frequency = <400000>; @@ -439,7 +446,6 @@ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - status = "okay"; }; /* diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index e2e9279fa267..8e3858cf988c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -112,7 +112,7 @@ &i2c1 { es8388: es8388@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi new file mode 100644 index 000000000000..ea051362fb26 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + arm { + /omit-if-no-ref/ + arm_pins: arm-pins { + rockchip,pins = + /* arm_avs */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clkm0_32k_out: clkm0-32k-out { + rockchip,pins = + /* clkm0_32k_out */ + <3 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clkm1_32k_out: clkm1-32k-out { + rockchip,pins = + /* clkm1_32k_out */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + eth_pins: eth-pins { + rockchip,pins = + /* eth_clk_25m_out */ + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + fephy { + /omit-if-no-ref/ + fephym0_led_dpx: fephym0-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_link: fephym0-led_link { + rockchip,pins = + /* fephy_led_link_m0 */ + <4 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_spd: fephym0-led_spd { + rockchip,pins = + /* fephy_led_spd_m0 */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_dpx: fephym1-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_link: fephym1-led_link { + rockchip,pins = + /* fephy_led_link_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_spd: fephym1-led_spd { + rockchip,pins = + /* fephy_led_spd_m1 */ + <2 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD5 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmi_pins: hdmi-pins { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_hpd */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* hdmi_tx_sda */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + hsm { + /omit-if-no-ref/ + hsmm0_pins: hsmm0-pins { + rockchip,pins = + /* hsm_clk_out_m0 */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hsmm1_pins: hsmm1-pins { + rockchip,pins = + /* hsm_clk_out_m1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <4 RK_PC4 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <4 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PA1 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PA0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <4 RK_PA3 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <4 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PC5 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PC6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <1 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <1 RK_PA6 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PA0 2 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PC1 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_scl */ + <2 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda */ + <2 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <1 RK_PB2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <1 RK_PB3 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PD2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <3 RK_PB2 5 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <3 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PD4 3 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7_xfer: i2c7-xfer { + rockchip,pins = + /* i2c7_scl */ + <2 RK_PA5 4 &pcfg_pull_none_smt>, + /* i2c7_sda */ + <2 RK_PA6 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi: i2s0m0-sdi { + rockchip,pins = + /* i2s0m0_sdi */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m0_sdo: i2s0m0-sdo { + rockchip,pins = + /* i2s0m0_sdo */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi: i2s0m1-sdi { + rockchip,pins = + /* i2s0m1_sdi */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m1_sdo: i2s0m1-sdo { + rockchip,pins = + /* i2s0m1_sdo */ + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1_lrck: i2s1-lrck { + rockchip,pins = + /* i2s1_lrck */ + <4 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_mclk: i2s1-mclk { + rockchip,pins = + /* i2s1_mclk */ + <4 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sclk: i2s1-sclk { + rockchip,pins = + /* i2s1_sclk */ + <4 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sdi0: i2s1-sdi0 { + rockchip,pins = + /* i2s1_sdi0 */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi1: i2s1-sdi1 { + rockchip,pins = + /* i2s1_sdi1 */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi2: i2s1-sdi2 { + rockchip,pins = + /* i2s1_sdi2 */ + <4 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi3: i2s1-sdi3 { + rockchip,pins = + /* i2s1_sdi3 */ + <4 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo0: i2s1-sdo0 { + rockchip,pins = + /* i2s1_sdo0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo1: i2s1-sdo1 { + rockchip,pins = + /* i2s1_sdo1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo2: i2s1-sdo2 { + rockchip,pins = + /* i2s1_sdo2 */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo3: i2s1-sdo3 { + rockchip,pins = + /* i2s1_sdo3 */ + <4 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_tck_m0 */ + <2 RK_PA2 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m0 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* jtag_mcu_tms_m0 */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_tck_m1 */ + <4 RK_PD0 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m1 */ + <4 RK_PC7 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m1 */ + <4 RK_PD0 3 &pcfg_pull_none>, + /* jtag_mcu_tms_m1 */ + <4 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pcie { + /omit-if-no-ref/ + pciem0_pins: pciem0-pins { + rockchip,pins = + /* pcie_clkreqn_m0 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* pcie_perstn_m0 */ + <3 RK_PB0 5 &pcfg_pull_none>, + /* pcie_waken_m0 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pciem1_pins: pciem1-pins { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie_perstn_m1 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie_waken_m1 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdm_clk0: pdm-clk0 { + rockchip,pins = + /* pdm_clk0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_clk1: pdm-clk1 { + rockchip,pins = + /* pdm_clk1 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + /* pdm_sdi0 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + /* pdm_sdi1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + /* pdm_sdi2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + /* pdm_sdi3 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <4 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + refm0_pins: refm0-pins { + rockchip,pins = + /* ref_clk_out_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + refm1_pins: refm1-pins { + rockchip,pins = + /* ref_clk_out_m1 */ + <3 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmii_miim: rgmii-miim { + rockchip,pins = + /* rgmii_mdc */ + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_mdio */ + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rx_bus2: rgmii-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_rxdv_crs */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_tx_bus2: rgmii-tx_bus2 { + rockchip,pins = + /* rgmii_txd0 */ + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd1 */ + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txen */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_clk: rgmii-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_bus: rgmii-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_txd2 */ + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd3 */ + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_clk: rgmii-clk { + rockchip,pins = + /* rgmii_clk */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmii_txer: rgmii-txer { + rockchip,pins = + /* rgmii_txer */ + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scrm0_pins: scrm0-pins { + rockchip,pins = + /* scr_clk_m0 */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_data_m0 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* scr_detn_m0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* scr_rstn_m0 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + scrm1_pins: scrm1-pins { + rockchip,pins = + /* scr_clk_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* scr_data_m1 */ + <2 RK_PA3 4 &pcfg_pull_none>, + /* scr_detn_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* scr_rstn_m1 */ + <2 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + sdio0 { + /omit-if-no-ref/ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + /* sdio0_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_clk: sdio0-clk { + rockchip,pins = + /* sdio0_clk */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_cmd: sdio0-cmd { + rockchip,pins = + /* sdio0_cmd */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_det: sdio0-det { + rockchip,pins = + /* sdio0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio0_pwren: sdio0-pwren { + rockchip,pins = + /* sdio0_pwren */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio1 { + /omit-if-no-ref/ + sdio1_bus4: sdio1-bus4 { + rockchip,pins = + /* sdio1_d0 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d1 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d2 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d3 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_clk: sdio1-clk { + rockchip,pins = + /* sdio1_clk */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_cmd: sdio1-cmd { + rockchip,pins = + /* sdio1_cmd */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_det: sdio1-det { + rockchip,pins = + /* sdio1_det */ + <3 RK_PB3 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio1_pwren: sdio1-pwren { + rockchip,pins = + /* sdio1_pwren */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_detn */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_pins: spi0-pins { + rockchip,pins = + /* spi0_clk */ + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>, + /* spi0_miso */ + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>, + /* spi0_mosi */ + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi0_csn0: spi0-csn0 { + rockchip,pins = + /* spi0_csn0 */ + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi0_csn1: spi0-csn1 { + rockchip,pins = + /* spi0_csn1 */ + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_pins: spi1-pins { + rockchip,pins = + /* spi1_clk */ + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* spi1_miso */ + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>, + /* spi1_mosi */ + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi1_csn0: spi1-csn0 { + rockchip,pins = + /* spi1_csn0 */ + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi1_csn1: spi1-csn1 { + rockchip,pins = + /* spi1_csn1 */ + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsi0 { + /omit-if-no-ref/ + tsi0_pins: tsi0-pins { + rockchip,pins = + /* tsi0_clkin */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* tsi0_d0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* tsi0_d1 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* tsi0_d2 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* tsi0_d3 */ + <3 RK_PB7 3 &pcfg_pull_none>, + /* tsi0_d4 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* tsi0_d5 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* tsi0_d6 */ + <3 RK_PA1 3 &pcfg_pull_none>, + /* tsi0_d7 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* tsi0_fail */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* tsi0_sync */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* tsi0_valid */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + tsi1 { + /omit-if-no-ref/ + tsi1_pins: tsi1-pins { + rockchip,pins = + /* tsi1_clkin */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* tsi1_d0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* tsi1_sync */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* tsi1_valid */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <4 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <4 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <4 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <4 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PC6 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PC5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1_ctsn: uart1-ctsn { + rockchip,pins = + /* uart1_ctsn */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1_rtsn: uart1-rtsn { + rockchip,pins = + /* uart1_rtsn */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PA0 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <1 RK_PB0 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <1 RK_PB1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB0 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <4 RK_PB7 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <4 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <2 RK_PA2 3 &pcfg_pull_up>, + /* uart4_tx */ + <2 RK_PA3 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PA2 2 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PA3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD4 2 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD7 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <3 RK_PC1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6_ctsn: uart6-ctsn { + rockchip,pins = + /* uart6_ctsn */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6_rtsn: uart6-rtsn { + rockchip,pins = + /* uart6_rtsn */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <1 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index d2cdb63d4a9d..57a446b5cbd6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -6,17 +6,150 @@ */ /dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "rk3528.dtsi" / { model = "Radxa E20C"; compatible = "radxa,e20c", "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + }; + chosen { stdout-path = "serial0:1500000n8"; }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_key>; + + button-user { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "USER"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>; + + led-lan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-sys { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&pinctrl { + gpio-keys { + user_key: user-key { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + lan_led_g: lan-led-g { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_g: sys-led-g { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_g: wan-led-g { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index e58faa985aa4..26c3559d6a6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -4,8 +4,12 @@ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> */ +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rockchip,rk3528-cru.h> +#include <dt-bindings/reset/rockchip,rk3528-cru.h> / { compatible = "rockchip,rk3528"; @@ -15,6 +19,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -51,6 +60,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu1: cpu@1 { @@ -58,6 +68,7 @@ reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu2: cpu@2 { @@ -65,6 +76,7 @@ reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu3: cpu@3 { @@ -72,6 +84,22 @@ reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; }; @@ -80,6 +108,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -95,6 +135,13 @@ #clock-cells = <0>; }; + gmac0_clk: clock-gmac50m { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac0"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,10 +161,219 @@ #interrupt-cells = <3>; }; + qos_crypto_a: qos@ff200000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200000 0x0 0x20>; + }; + + qos_crypto_p: qos@ff200080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200080 0x0 0x20>; + }; + + qos_dcf: qos@ff200100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200100 0x0 0x20>; + }; + + qos_dft2apb: qos@ff200200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200200 0x0 0x20>; + }; + + qos_dma2ddr: qos@ff200280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200280 0x0 0x20>; + }; + + qos_dmac: qos@ff200300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200300 0x0 0x20>; + }; + + qos_keyreader: qos@ff200380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200380 0x0 0x20>; + }; + + qos_cpu: qos@ff210000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210000 0x0 0x20>; + }; + + qos_debug: qos@ff210080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210080 0x0 0x20>; + }; + + qos_gpu_m0: qos@ff220000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220000 0x0 0x20>; + }; + + qos_gpu_m1: qos@ff220080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220080 0x0 0x20>; + }; + + qos_pmu_mcu: qos@ff240000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff240000 0x0 0x20>; + }; + + qos_rkvdec: qos@ff250000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff250000 0x0 0x20>; + }; + + qos_rkvenc: qos@ff260000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff260000 0x0 0x20>; + }; + + qos_gmac0: qos@ff270000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270000 0x0 0x20>; + }; + + qos_hdcp: qos@ff270080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270080 0x0 0x20>; + }; + + qos_jpegdec: qos@ff270100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270100 0x0 0x20>; + }; + + qos_rga2_m0ro: qos@ff270200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270200 0x0 0x20>; + }; + + qos_rga2_m0wo: qos@ff270280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270280 0x0 0x20>; + }; + + qos_sdmmc0: qos@ff270300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270300 0x0 0x20>; + }; + + qos_usb2host: qos@ff270380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270380 0x0 0x20>; + }; + + qos_vdpp: qos@ff270480 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270480 0x0 0x20>; + }; + + qos_vop: qos@ff270500 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270500 0x0 0x20>; + }; + + qos_emmc: qos@ff280000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280000 0x0 0x20>; + }; + + qos_fspi: qos@ff280080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280080 0x0 0x20>; + }; + + qos_gmac1: qos@ff280100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280100 0x0 0x20>; + }; + + qos_pcie: qos@ff280180 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280180 0x0 0x20>; + }; + + qos_sdio0: qos@ff280200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280200 0x0 0x20>; + }; + + qos_sdio1: qos@ff280280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280280 0x0 0x20>; + }; + + qos_tsp: qos@ff280300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280300 0x0 0x20>; + }; + + qos_usb3otg: qos@ff280380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280380 0x0 0x20>; + }; + + qos_vpu: qos@ff280400 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280400 0x0 0x20>; + }; + + cru: clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks = + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates = + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ioc_grf: syscon@ff540000 { + compatible = "rockchip,rk3528-ioc-grf", "syscon"; + reg = <0x0 0xff540000 0x0 0x40000>; + }; + uart0: serial@ff9f0000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f0000 0x0 0x100>; - clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -127,6 +383,8 @@ uart1: serial@ff9f8000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f8000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -136,6 +394,8 @@ uart2: serial@ffa00000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa00000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -144,6 +404,8 @@ uart3: serial@ffa08000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; reg = <0x0 0xffa08000 0x0 0x100>; reg-io-width = <4>; reg-shift = <2>; @@ -153,6 +415,8 @@ uart4: serial@ffa10000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa10000 0x0 0x100>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -162,6 +426,8 @@ uart5: serial@ffa18000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa18000 0x0 0x100>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -171,6 +437,8 @@ uart6: serial@ffa20000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa20000 0x0 0x100>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -180,10 +448,118 @@ uart7: serial@ffa28000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa28000 0x0 0x100>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; + + saradc: adc@ffae0000 { + compatible = "rockchip,rk3528-saradc"; + reg = <0x0 0xffae0000 0x0 0x10000>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc", + "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, + <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_strb>; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; }; + +#include "rk3528-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 2d3ae1544822..3613661417b2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -9,6 +9,8 @@ #include "rk3566.dtsi" / { + chassis-type = "tablet"; + aliases { mmc0 = &sdhci; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 98e75df8b158..3c127c5c2607 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -265,8 +265,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-supply = <&vcc_3v3>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 24928a129446..5707321a1144 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -173,8 +173,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts new file mode 100644 index 000000000000..58c1052ba8ef --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <6800000>; + energy-full-design-microwatt-hours = <25000000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = <4100000 100>, <4040000 90>, + <3980000 80>, <3920000 70>, + <3870000 60>, <3820000 50>, + <3790000 40>, <3770000 30>, + <3740000 20>, <3680000 10>, + <3450000 0>; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi_con: hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* actually fed by vcc_syson, dependent + * on pi6c clock generator + */ + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c: regulator-vcc3v3-pi6c { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwren>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v4_rf: regulator-vcc3v4-rf { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rf_pwr_en>; + regulator-name = "vcc3v4_rf"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + vin-supply = <&vccin_5v>; + }; + + vcc5v0_usb30_otg0: regulator-vcc5v0-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vccin_5v: regulator-vccin-5v { + compatible = "regulator-fixed"; + regulator-name = "vccin_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vcc_syson: regulator-vcc-syson { + compatible = "regulator-fixed"; + regulator-name = "vcc_syson"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcca_1v8: regulator-vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: regulator-vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_gpu: regulator-vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + rfkill-modem { + compatible = "rfkill-gpio"; + label = "M.2 USB Modem"; + radio-type = "wwan"; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h &clk32k_out1>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* Motorcomm YT8521SC LAN port (require SGMII) */ +&gmac0 { + status = "disabled"; +}; + +/* Motorcomm YT8521SC WAN port */ +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_syson>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +/* M.2 E-Key for PCIe WLAN */ +&pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + rf_pwr_en: rf-pwr-en { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* Micro SD card slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 WiFi */ +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 Bluetooth */ +&uart1 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&pmucru CLK_RTC_32K>; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>; + vddio-supply = <&vcc_1v8>; + }; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +&uart3 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* Onboard power management MCU */ +&uart4 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* M.2 E-Key for USB Bluetooth */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-A Port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* M.2 B-Key for USB Modem WWAN */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc3v4_rf>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&xin32k { + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out1>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ac79140a9ecd..44cfdfeed668 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -778,20 +778,6 @@ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; }; &uart2 { diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 4e730aecf84d..fd2214b6fad4 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -174,6 +174,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, @@ -199,19 +211,6 @@ #clock-cells = <0>; }; - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - sata1: sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; reg = <0 0xfc400000 0 0x1000>; @@ -1044,6 +1043,11 @@ status = "disabled"; }; + /* + * Testing showed that the HWRNG found in RK3566 produces unacceptably + * low quality of random data, so the HWRNG isn't enabled for all RK356x + * SoC variants despite its presence. + */ rng: rng@fe388000 { compatible = "rockchip,rk3568-rng"; reg = <0x0 0xfe388000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 7c7331936a7f..828bde7fab68 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -10,6 +10,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/usb/pd.h> #include "rk3576.dtsi" @@ -26,6 +27,17 @@ stdout-path = "serial0:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -182,8 +194,7 @@ ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay"; @@ -214,6 +225,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -656,3 +687,18 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 782ca000a644..e368691fd28e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -10,6 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3576.dtsi" / { @@ -57,6 +58,17 @@ }; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -270,6 +282,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -729,3 +761,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts new file mode 100644 index 000000000000..612b7bb0b749 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Firefly Technology Co. Ltd + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Firefly ROC-RK3576-PC"; + compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <17000>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5vd_en>; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren_h>; + regulator-name = "vcc5v0_host1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy0>; + tx_delay = <0x21>; + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + /* Reset time is 20ms, 100ms for rtl8211f */ + reset-delay-us = <20000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100000>; + }; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + /* hnyetek,husb311 typec-portc@4e */ + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc5vd_en: vcc5vd-en { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + hub_reset_h: hub-reset-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb3_host_pwren_h: usb3-host-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int_l: usbc0-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + watchdog { + wd_en: wd-en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; + status = "okay"; +}; + +/* On the extension pin header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m3_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts new file mode 100644 index 000000000000..6756403111e7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Radxa ROCK 4D"; + compatible = "radxa,rock-4d", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g &led_rgb_r>; + + power-led { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc_12v0_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc_1v2_ufs_vccq_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_ufs_vccq2_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_pcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_rtc_s5"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_ufs_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_device"; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc_5v0_device>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_sys"; + vin-supply = <&vcc_12v0_dcin>; + }; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_g: led-green-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-red-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren: pcie-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&sfc0 { + pinctrl-names = "default"; + pinctrl-0 = <&fspi0_pins &fspi0_csn0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index bd55bd8a67cb..ebb5fc8bb8b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -111,7 +111,7 @@ reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <120>; @@ -124,7 +124,7 @@ reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -135,7 +135,7 @@ reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -146,7 +146,7 @@ reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -157,7 +157,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <320>; @@ -170,7 +170,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -181,7 +181,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -192,7 +192,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -393,6 +393,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -620,6 +625,11 @@ }; }; + hdptxphy_grf: syscon@26032000 { + compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; + reg = <0x0 0x26032000 0x0 0x100>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -922,7 +932,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; @@ -937,6 +947,109 @@ status = "disabled"; }; + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", + "vp0", + "vp1", + "vp2"; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, + <&cru DCLK_VP2>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; + }; + + vop_mmu: iommu@27d07e00 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3576_PD_VOP>; + status = "disabled"; + }; + + hdmi: hdmi@27da0000 { + compatible = "rockchip,rk3576-dw-hdmi-qp"; + reg = <0x0 0x27da0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_SAI6_8CH>, + <&cru CLK_HDMITXHDP>, + <&cru HCLK_VO0_ROOT>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; + reset-names = "ref", "hdp"; + rockchip,grf = <&ioc_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + qos_hdcp1: qos@27f02000 { compatible = "rockchip,rk3576-qos", "syscon"; reg = <0x0 0x27f02000 0x0 0x20>; @@ -1245,6 +1358,17 @@ status = "disabled"; }; + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>; @@ -1284,6 +1408,56 @@ status = "disabled"; }; + sfc0: spi@2a340000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a340000 0x0 0x4000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, @@ -1780,6 +1954,19 @@ status = "disabled"; }; + hdptxphy: hdmiphy@2b000000 { + compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi index a3138d2d384c..e44125e9a8fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi @@ -114,6 +114,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 08f09053a066..ae9274365bed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3588.dtsi" / { @@ -33,6 +34,17 @@ "Headphone", "Headphones"; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -164,6 +176,30 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -258,6 +294,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + /* phy1 - right ethernet port */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -268,6 +308,22 @@ &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ @@ -286,6 +342,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -723,3 +783,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index c3abdfb04f8f..1e18ad93ba0e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -358,11 +358,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - scmi: scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0x82000010>; @@ -382,6 +377,22 @@ }; }; + hdmi0_sound: hdmi0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi0"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; @@ -864,7 +875,7 @@ }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg = <RK3588_PD_GPU>; clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, @@ -1261,14 +1272,16 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; @@ -1318,6 +1331,21 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + dma-names = "tx"; + dmas = <&dmac1 6>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1335,6 +1363,21 @@ status = "disabled"; }; + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + dma-names = "tx"; + dmas = <&dmac1 7>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s5_8ch: i2s@fddf0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf0000 0x0 0x1000>; @@ -1385,7 +1428,7 @@ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; pinctrl-names = "default"; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -1394,6 +1437,7 @@ reset-names = "ref", "hdp"; rockchip,grf = <&sys_grf>; rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -1921,6 +1965,14 @@ status = "disabled"; }; + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset 48>; + }; + i2s0_8ch: i2s@fe470000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfe470000 0x0 0x1000>; @@ -2016,12 +2068,47 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + dma-names = "tx"; + dmas = <&dmac0 5>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif0m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + dma-names = "tx"; + dmas = <&dmac1 5>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif1m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ <0x0 0xfe680000 0 0x100000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; + dma-noncoherent; mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; @@ -2033,6 +2120,7 @@ its0: msi-controller@fe640000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe640000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2040,6 +2128,7 @@ its1: msi-controller@fe660000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe660000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2807,11 +2896,12 @@ #dma-cells = <1>; }; - hdptxphy_hdmi0: phy@fed60000 { + hdptxphy0: phy@fed60000 { compatible = "rockchip,rk3588-hdptx-phy"; reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 9d525c8ff725..9eda69722665 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -129,7 +129,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts index bc6b43a77153..6dc10da5215f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -166,7 +166,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index 71ed680621b8..cc37f082adea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 5e72d0eff0e0..8a783dc64c0e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -126,6 +126,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_user_en: led_user_en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 7125790bbed2..08920344a4b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -4,12 +4,24 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/soc/rockchip,vop2.h> / { chosen { stdout-path = "serial2:1500000n8"; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -81,6 +93,26 @@ status = "okay"; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -275,3 +307,18 @@ &usb_host2_xhci { status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ba49f0bbaac6..8e912da299a2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -132,6 +132,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { compatible = "regulator-fixed"; regulator-name = "pcie20_avdd0v85"; @@ -364,7 +375,27 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -441,7 +472,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -519,6 +550,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { @@ -1371,11 +1406,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -1385,3 +1420,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 840b638af1c2..099edb3fd0f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -7,6 +7,46 @@ #include "rk3588-extra-pinctrl.dtsi" / { + hdmi1_sound: hdmi1-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi1"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi1>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s6_8ch>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + * The size of 160MB was determined as follows: + * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB + * To ensure sufficient support for practical use-cases, + * we doubled the 66MB value. + */ + hdmi_receiver_cma: hdmi-receiver-cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + alignment = <0x0 0x40000>; /* 64K */ + no-map; + status = "disabled"; + }; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -67,6 +107,26 @@ }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + dma-names = "tx"; + dmas = <&dmac1 22>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -84,6 +144,21 @@ status = "disabled"; }; + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + dma-names = "tx"; + dmas = <&dmac1 8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s6_8ch: i2s@fddf4000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf4000 0x0 0x1000>; @@ -135,6 +210,79 @@ status = "disabled"; }; + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfdea0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru CLK_HDMIHDP1>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + }; + + hdmi1_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_receiver: hdmi_receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + memory-region = <&hdmi_receiver_cma>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -398,6 +546,23 @@ }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>; @@ -449,3 +614,24 @@ status = "disabled"; }; }; + +&vop { + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi index 390051317389..4331cdc70f97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -205,6 +205,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_rgb_b: led-rgb-b { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi index 42c523b553c9..80e16ea4154c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi @@ -108,6 +108,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 000000000000..6726eeb49255 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts index 2be5251d3e3b..e086114c7634 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts @@ -337,7 +337,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index b3a04ca370bb..8171fbfd819a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -335,7 +335,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99fc..1af0a30866f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -256,6 +256,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts index 4791b77f3571..73d8ce4fde2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts @@ -140,6 +140,24 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &combphy0_ps { @@ -207,7 +225,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -316,6 +334,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -400,6 +422,12 @@ status = "okay"; }; +&spdif_tx0 { + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m1_tx>; + status = "okay"; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso new file mode 100644 index 000000000000..9d44dfe2f30d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 Cherry Embedded Solutions GmbH + * + * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine + * connector on RK3588 Jaguar. + * + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary + * camera connectors (each their own I2C bus, clock, reset and PWM lines as well + * as 2-lane CSI). + * + * This adapter routes some GPIOs to power rails and loops together some other + * GPIOs. + * + * This adapter is used during manufacturing for validating proper soldering of + * the mezzanine connector. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3_s3>; + }; + + pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gpio3 { + pinctrl-0 = <&pre_ict_pwr2gpio>; + pinctrl-names = "default"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1l2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */ + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pinctrl { + pcie2x1l2 { + pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pre-ict-tester { + pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins { + rockchip,pins = + /* + * GPIO3_A3 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_2 is properly routed, GPIO3_A3 should be + * LOW. The signal shall not read HIGH in the event + * GPIO3_A3 isn't properly routed due to soldering + * issue. Therefore, let's enforce a pull-up (which is + * the SoC default for this pin). + */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power + * rail. It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_B2 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_1 is properly routed, GPIO3_B2 should be + * LOW. This is an issue if GPIO3_B2 isn't properly + * routed due to soldering issue, because GPIO3_B2 + * default bias is pull-down therefore being LOW. So + * the worst case scenario and the pass scenario expect + * the same value. Make GPIO3_B2 a pull-up so that a + * soldering issue on GPIO3_B2 reports HIGH but proper + * soldering reports LOW. + */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power + * rail. It should be HIGH if all is properly soldered. + * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't + * properly routed due to soldering issue, because + * GPIO3_C6 default bias is pull-up therefore being HIGH + * in all cases: + * - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not + * routed properly, + * - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is + * not routed properly, + * - GPIO3_C6 is HIGH if everything is proper, + * Make GPIO3_C6 a pull-down so that a soldering issue + * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper + * soldering reports HIGH. + */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D2 is routed to VCC_5V0_1 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D3 is routed to VCC_5V0_2 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 7f457ab78015..9fceea6c1398 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -303,7 +303,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -333,6 +333,56 @@ }; }; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int1>; + vbus-supply = <&vcc_5v0_usb_c1>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-1 P11"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + vdd_npu_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -394,6 +444,56 @@ pinctrl-0 = <&i2c8m2_xfer>; status = "okay"; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int2>; + vbus-supply = <&vcc_5v0_usb_c2>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-2 P12"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc1_hs: endpoint { + remote-endpoint = <&usb_host1_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc1_ss: endpoint { + remote-endpoint = <&usbdp_phy1_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc1_sbu: endpoint { + remote-endpoint = <&usbdp_phy1_typec_sbu>; + }; + }; + }; + }; + }; + vdd_cpu_big0_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -451,6 +551,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -483,6 +587,26 @@ rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; }; }; + + usb3 { + cc_int1: cc-int1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cc_int2: cc-int2 { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec0_sbu_dc_pins: typec0-sbu-dc-pins { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + typec1_sbu_dc_pins: typec1-sbu-dc-pins { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &saradc { @@ -850,6 +974,24 @@ status = "okay"; }; +/* USB-C P11 connector */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +/* USB-C P12 connector */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -892,6 +1034,56 @@ status = "okay"; }; +/* Type-C on P11 */ +&usbdp_phy0 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec0_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +/* Type-C on P12 */ +&usbdp_phy1 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec1_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy1_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_ss>; + }; + + usbdp_phy1_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc1_sbu>; + }; + }; +}; + /* host0 on P10 USB-A */ &usb_host0_ehci { status = "okay"; @@ -902,6 +1094,36 @@ status = "okay"; }; +/* host0 on P11 USB-C */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +/* host1 on P12 USB-C */ +&usb_host1_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host1_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc1_hs>; + }; + }; +}; + /* host1 on M.2 E-key */ &usb_host1_ehci { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 000000000000..78a4e896f665 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm8 0 10000 0>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <40000000>; + no-1-8-v; + no-mmc; + no-sdio; + vmmc-supply = <&vcc3v3_pcie30>; + vqmmc-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index cb350727d116..bbe500cc924b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -360,7 +360,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -565,6 +565,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 1c0851b45eb8..fbe1d5c06d90 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi index 87090cb98020..f748c6f760d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi @@ -7,9 +7,6 @@ #include "rk3588-orangepi-5.dtsi" / { - model = "Xunlong Orange Pi 5 Max"; - compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; - vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -62,18 +59,12 @@ &led_blue_pwm { /* PWM_LED1 */ - pwms = <&pwm4 0 25000 0>; status = "okay"; }; -&led_green_pwm { - /* PWM_LED2 */ - pwms = <&pwm5 0 25000 0>; -}; - /* phy2 */ &pcie2x1l1 { - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie_eth>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts index ce44549babf4..8b1d35760c3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts @@ -21,6 +21,17 @@ }; }; }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; }; &hdmi0 { @@ -39,10 +50,57 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { status = "okay"; }; +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 0>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 0>; +}; + &pinctrl { usb { @@ -58,3 +116,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 255e33c5dbdc..121e4d1c3fa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -26,6 +26,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; @@ -113,6 +124,10 @@ status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -125,7 +140,31 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -189,6 +228,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_gpio { gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -342,3 +389,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts new file mode 100644 index 000000000000..f8c6c080e418 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588-orangepi-5-compact.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Ultra"; + compatible = "xunlong,orangepi-5-ultra", "rockchip,rk3588"; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; +}; + +&pinctrl { + usb { + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_usb30_otg { + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi index a98e804a0949..91d56c34a1e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi @@ -276,7 +276,7 @@ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -348,6 +348,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 088cfade6f6f..78aaa6635b5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -311,7 +311,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; @@ -347,6 +347,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 2a0590209462..7de17117df7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -11,6 +11,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "dt-bindings/usb/pd.h" #include "rk3588.dtsi" @@ -72,6 +73,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -261,6 +273,28 @@ status = "okay"; }; +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -564,6 +598,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { @@ -1208,3 +1246,18 @@ rockchip,dp-lane-mux = <2 3>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index d597112f1d5b..d22068475c5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -49,6 +49,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -220,7 +231,48 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -318,6 +370,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -376,7 +436,17 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -891,11 +961,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -905,3 +975,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 3187b4918a30..a3d8ff647839 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -189,7 +189,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -310,8 +310,10 @@ status = "okay"; }; +/* DB9 RS232/RS485 when SW2 in "UART1" mode */ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &usbdp_phy0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index e8fa449517c2..c4933a08dd1e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -173,7 +173,6 @@ &i2c2 { pinctrl-0 = <&i2c2m3_xfer>; - status = "okay"; }; &i2c2m3_xfer { @@ -336,6 +335,10 @@ reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 3cbee5b97470..5a428e00ab93 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -289,6 +289,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { rtl8211f { rtl8211f_rst: rtl8211f-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6bc46734cc14..711ac4f2c7cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -287,6 +287,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 9c394f733bbf..8b717c4017a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -236,7 +236,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -361,6 +361,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -429,7 +433,7 @@ }; &pwm13 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm13m2_pins>; status = "okay"; }; @@ -803,6 +807,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -832,6 +844,16 @@ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; }; +&usbdp_phy0 { + /* + * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally + * the differential pairs 0+1 and the aux channel are wired to a + * mini DP connector. + */ + rockchip,dp-lane-mux = <0 1>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; @@ -840,6 +862,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&u2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index bc4077575beb..9f4aca9c2e3f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -242,7 +242,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -340,6 +340,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 812bba0aef1a..873a2bd6a6de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -611,7 +611,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -675,6 +675,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 4a3aa80f2226..4189a88ecf40 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -412,7 +412,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -455,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index ac48e7fd3923..88a5e822ed17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index d2eddea1840f..fbf062ec3bf1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,7 +251,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts index 8f034c6d494c..a72063c55140 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts @@ -264,7 +264,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -433,6 +433,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { lcd { lcd_pwren: lcd-pwren { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index d86aeacca238..4fedc50cce8c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -197,7 +197,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -268,7 +272,7 @@ status = "okay"; es8388: audio-codec@10 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x10>; clocks = <&cru I2S1_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -355,6 +359,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -365,6 +373,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 70a43432bdc5..f894742b1ebe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -334,7 +334,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { io_led: io-led { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index 9b14d5383cdc..dd7317bab613 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -68,10 +68,10 @@ }; }; - fan { + fan: fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-levels = <0 64 128 192 255>; + cooling-levels = <0 24 44 64 128 192 255>; fan-supply = <&vcc_5v0>; pwms = <&pwm3 0 10000 0>; }; @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -417,6 +417,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l2 { pinctrl-names = "default"; pinctrl-0 = <&pcie20x1_2_perstn_m0>; @@ -425,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_pins: led-pins { @@ -843,6 +877,8 @@ }; &tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ status = "okay"; }; diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 881fe1296c58..63908113ae36 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp215f-dk.dtb \ + stm32mp235f-dk.dtb \ + stm32mp257f-dk.dtb \ + stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi new file mode 100644 index 000000000000..6dd1377f3e1d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + + ck_flexgen_08: clock-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: clock-200000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x0 0x80000000>; + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <2>; + + rifsc: bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x0 0x1000>; + ranges; + dma-ranges; + #address-cells = <1>; + #size-cells = <2>; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x0 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp21-syscfg", "syscon"; + reg = <0x44230000 0x0 0x10000>; + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x4ac10000 0x0 0x1000>, + <0x4ac20000 0x0 0x2000>, + <0x4ac40000 0x0 0x2000>, + <0x4ac60000 0x0 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi new file mode 100644 index 000000000000..fdd2dc432edd --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp211.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi new file mode 100644 index 000000000000..a7df77f928c5 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp213.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts new file mode 100644 index 000000000000..7bdaeaa5ab0f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp215.dtsi" +#include "stm32mp21xf.dtsi" + +/ { + model = "STMicroelectronics STM32MP215F-DK Discovery Board"; + compatible = "st,stm32mp215f-dk", "st,stm32mp215"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xf.dtsi b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi new file mode 100644 index 000000000000..8820d219a33e --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -0,0 +1,1214 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/clock/st,stm32mp25-rcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/regulator/st,stm32mp25-regulator.h> +#include <dt-bindings/reset/st,stm32mp25-rcc.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu0_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clk_dsi_txbyte: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk_rcbsec: clk-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = <VOLTD_SCMI_VDDIO1>; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = <VOLTD_SCMI_VDDIO2>; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = <VOLTD_SCMI_VDDIO3>; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = <VOLTD_SCMI_VDDIO4>; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = <VOLTD_SCMI_UCPD>; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = <VOLTD_SCMI_ADC>; + regulator-name = "vdda18adc"; + }; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&ret_pd>; + }; + + ret_pd: power-domain-retention { + #power-domain-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x80000000>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + + i2s2: audio-controller@400b0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400b0000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x43 0x12>, + <&hpdma 52 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi2: spi@400b0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x20 0x3012>, + <&hpdma 52 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + i2s3: audio-controller@400c0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400c0000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x43 0x12>, + <&hpdma 54 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x20 0x3012>, + <&hpdma 54 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spdifrx: audio-controller@400d0000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x400d0000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SPDIFRX>; + clock-names = "kclk"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 71 0x43 0x212>, + <&hpdma 72 0x43 0x212>; + dma-names = "rx", "rx-ctrl"; + access-controllers = <&rifsc 30>; + status = "disabled"; + }; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART2>; + dmas = <&hpdma 11 0x20 0x10012>, + <&hpdma 12 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 32>; + status = "disabled"; + }; + + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART3>; + dmas = <&hpdma 13 0x20 0x10012>, + <&hpdma 14 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART4>; + dmas = <&hpdma 15 0x20 0x10012>, + <&hpdma 16 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART5>; + dmas = <&hpdma 17 0x20 0x10012>, + <&hpdma 18 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + dmas = <&hpdma 27 0x20 0x3012>, + <&hpdma 28 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + dmas = <&hpdma 30 0x20 0x3012>, + <&hpdma 31 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + dmas = <&hpdma 45 0x20 0x3012>, + <&hpdma 46 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART6>; + dmas = <&hpdma 19 0x20 0x10012>, + <&hpdma 20 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + + i2s1: audio-controller@40230000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x40230000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x43 0x12>, + <&hpdma 50 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi1: spi@40230000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x20 0x3012>, + <&hpdma 50 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + dmas = <&hpdma 55 0x20 0x3012>, + <&hpdma 56 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + dmas = <&hpdma 57 0x20 0x3012>, + <&hpdma 58 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + sai1: sai@40290000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; + ranges = <0 0x40290000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI1>; + clock-names = "pclk"; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + access-controllers = <&rifsc 49>; + status = "disabled"; + + sai1a: audio-controller@40290004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 73 0x43 0x21>; + status = "disabled"; + }; + + sai1b: audio-controller@40290024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 74 0x43 0x12>; + status = "disabled"; + }; + }; + + sai2: sai@402a0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; + ranges = <0 0x402a0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI2>; + clock-names = "pclk"; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + access-controllers = <&rifsc 50>; + status = "disabled"; + + sai2a: audio-controller@402a0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 75 0x43 0x21>; + status = "disabled"; + }; + + sai2b: audio-controller@402a0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 76 0x43 0x12>; + status = "disabled"; + }; + }; + + sai3: sai@402b0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; + ranges = <0 0x402b0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI3>; + clock-names = "pclk"; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI3_R>; + access-controllers = <&rifsc 51>; + status = "disabled"; + + sai3a: audio-controller@402b0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 77 0x43 0x21>; + status = "disabled"; + }; + + sai3b: audio-controller@502b0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 78 0x43 0x12>; + status = "disabled"; + }; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART1>; + dmas = <&hpdma 9 0x20 0x10012>, + <&hpdma 10 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + + sai4: sai@40340000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; + ranges = <0 0x40340000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI4>; + clock-names = "pclk"; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI4_R>; + access-controllers = <&rifsc 52>; + status = "disabled"; + + sai4a: audio-controller@40340004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 79 0x63 0x21>; + status = "disabled"; + }; + + sai4b: audio-controller@40340024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 80 0x43 0x12>; + status = "disabled"; + }; + }; + + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART7>; + dmas = <&hpdma 21 0x20 0x10012>, + <&hpdma 22 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + rng: rng@42020000 { + compatible = "st,stm32mp25-rng"; + reg = <0x42020000 0x400>; + clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; + clock-names = "core", "bus"; + resets = <&rcc RNG_R>; + access-controllers = <&rifsc 92>; + status = "disabled"; + }; + + spi8: spi@46020000 { + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + dmas = <&hpdma 171 0x20 0x3012>, + <&hpdma 172 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + dmas = <&hpdma 168 0x20 0x3012>, + <&hpdma 169 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + + csi: csi@48020000 { + compatible = "st,stm32mp25-csi"; + reg = <0x48020000 0x2000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CSI_R>; + clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, + <&rcc CK_KER_CSIPHY>; + clock-names = "pclk", "txesc", "csi2phy"; + access-controllers = <&rifsc 86>; + status = "disabled"; + }; + + dcmipp: dcmipp@48030000 { + compatible = "st,stm32mp25-dcmipp"; + reg = <0x48030000 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc DCMIPP_R>; + clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; + clock-names = "kclk", "mclk"; + access-controllers = <&rifsc 87>; + status = "disabled"; + }; + + sdmmc1: mmc@48220000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + reg = <0x48220000 0x400>, <0x44230400 0x8>; + arm,primecell-periphid = <0x00353180>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC1 >; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + access-controllers = <&rifsc 76>; + status = "disabled"; + }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + }; + + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; + }; + + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x44220000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_80 */ + <0>, + <0>, + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp23-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@44240000 { + reg = <0x0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + reg = <0x10000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + reg = <0x20000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + reg = <0x30000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + reg = <0x40000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + reg = <0x50000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + reg = <0x60000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + reg = <0x70000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + reg = <0x80000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + reg = <0x90000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + reg = <0xa0000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + rtc: rtc@46000000 { + compatible = "st,stm32mp25-rtc"; + reg = <0x46000000 0x400>; + clocks = <&scmi_clk CK_SCMI_RTC>, + <&scmi_clk CK_SCMI_RTCCK>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pinctrl_z: pinctrl@46200000 { + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioz: gpio@46200000 { + reg = <0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x46230000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <0>, + <0>, + <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x4ac10000 0x1000>, + <0x4ac20000 0x2000>, + <0x4ac40000 0x2000>, + <0x4ac60000 0x2000>; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp233.dtsi b/arch/arm64/boot/dts/st/stm32mp233.dtsi new file mode 100644 index 000000000000..78f4059fca5d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp233.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp231.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + reg = <1>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu1_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + cpu1_pd: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + }; + + timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&optee { + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi new file mode 100644 index 000000000000..2719c088dd59 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp233.dtsi" + +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_VDEC>; + access-controllers = <&rifsc 89>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts new file mode 100644 index 000000000000..04d1b434c433 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp235.dtsi" +#include "stm32mp23xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = <VOLTD_SCMI_STPMIC2_LDO7>; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xf.dtsi b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts new file mode 100644 index 000000000000..a278a1e3ce03 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = <VOLTD_SCMI_STPMIC2_LDO7>; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 690b4ed9c29b..9951eef9507c 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -92,7 +92,7 @@ reg = <0x0 0x000>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -108,7 +108,7 @@ reg = <0x0 0x001>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -124,7 +124,7 @@ reg = <0x0 0x002>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -139,7 +139,7 @@ compatible = "arm,cortex-a72"; reg = <0x0 0x003>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -156,7 +156,7 @@ reg = <0x0 0x100>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -172,7 +172,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -188,7 +188,7 @@ reg = <0x0 0x102>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -204,7 +204,7 @@ reg = <0x0 0x103>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -221,7 +221,7 @@ reg = <0x0 0x200>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -237,7 +237,7 @@ reg = <0x0 0x201>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -253,7 +253,7 @@ reg = <0x0 0x202>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -269,7 +269,7 @@ reg = <0x0 0x203>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -291,7 +291,7 @@ idle-states { entry-method = "psci"; - CPU_SLEEP: cpu-sleep { + cpu_sleep: cpu-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; local-timer-stop; diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8a4bdf87e2d4..03d4cecfc001 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -185,6 +186,8 @@ k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo +k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 2ef4cbaec789..55ed418c023b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -29,6 +29,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -36,15 +37,21 @@ #size-cells = <2>; ranges; - ramoops@9ca00000 { + ramoops@9c700000 { compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; + reg = <0x00 0x9c700000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; pmsg-size = <0x8000>; }; + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; @@ -131,6 +138,7 @@ AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -138,6 +146,7 @@ AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -153,6 +162,7 @@ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -170,6 +180,7 @@ AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -186,6 +197,7 @@ AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -210,6 +222,7 @@ &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -220,6 +233,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; @@ -232,10 +246,15 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -355,6 +374,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -363,5 +383,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 9202181fbd65..fcc4cb2e9389 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -28,10 +28,10 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", - "Headphone Jack", "MICBIAS", - "IN1L", "Headphone Jack"; + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; simple-audio-card,widgets = - "Microphone", "Headphone Jack", + "Microphone", "Microphone Jack", "Headphone", "Headphone Jack", "Line", "Line In Jack"; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 75c80290b12a..a5469f2712f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -65,6 +65,14 @@ pmsg-size = <0x8000>; }; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 0469c766b769..9ed9d703ff24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -12,7 +12,6 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - status = "disabled"; }; mcu_esm: esm@4100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index a5aceaa39670..147d56b87984 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -42,6 +42,7 @@ device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved-memory { @@ -99,6 +100,7 @@ AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -106,6 +108,7 @@ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -121,6 +124,7 @@ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -138,6 +142,7 @@ AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -155,6 +160,7 @@ AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -165,14 +171,15 @@ }; &cpsw3g { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; + status = "okay"; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -182,6 +189,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; @@ -196,6 +204,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -215,8 +224,8 @@ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; - ti,power-button; system-power-controller; + ti,power-button; regulators { vdd_3v3: buck1 { @@ -302,6 +311,10 @@ status = "okay"; }; +&main_pktdma { + bootph-all; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -318,6 +331,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -326,5 +340,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index a6f0d87a50d8..1c9d95696c83 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -18,10 +18,13 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + rtc1 = &tps659312; }; chosen { @@ -655,6 +658,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index b33aff0d65c9..bd6a00d13aea 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -12,15 +12,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - pinctrl-single,gpio-range = - <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; - - mcu_pmx_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; }; mcu_esm: esm@4100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6f32135f00a5..6757b37a9de3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -2,9 +2,11 @@ /* * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S * - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/bus/ti-sysc.h> + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; @@ -41,14 +43,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 420c77c8e9e5..6aea9d3f134e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -42,17 +42,23 @@ ti,interrupt-ranges = <5 69 35>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; +&main_conf { + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 16>; + #clock-cells = <0>; + }; - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 18>; + assigned-clocks = <&k3_clks 157 18>; + assigned-clock-parents = <&k3_clks 157 34>; + #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ad71d2f27f53..d29f524600af 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -19,6 +19,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; @@ -310,7 +311,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ >; }; @@ -519,6 +520,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi index 922cad14c9f8..aab74d6019b0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -138,6 +138,7 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; + bootph-all; }; vcc_3v3_sw: regulator-vcc-3v3-sw { @@ -233,6 +234,7 @@ AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; main_rgmii2_pins_default: main-rgmii2-default-pins { @@ -257,6 +259,7 @@ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -266,6 +269,7 @@ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ >; + bootph-pre-ram; }; main_usb1_pins_default: main-usb1-default-pins { @@ -430,12 +434,14 @@ &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; status = "okay"; }; &main_uart1 { pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; + bootph-pre-ram; /* Main UART1 may be used by TIFS firmware */ status = "okay"; }; @@ -467,11 +473,13 @@ pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; status = "okay"; }; &usbss0 { ti,vbus-divider; + bootph-all; status = "okay"; }; @@ -482,6 +490,7 @@ &usb0 { usb-role-switch; + bootph-all; port { typec_hs: endpoint { diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 2f129e8cd5b9..d52cb2a5a589 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -12,6 +12,8 @@ / { aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; mmc0 = &sdhci0; mmc1 = &sdhci1; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 99a6fdfaa7fb..d9d491b12c33 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -27,6 +27,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -99,6 +100,12 @@ reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; leds { @@ -132,6 +139,7 @@ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ >; + bootph-all; }; cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { @@ -150,6 +158,7 @@ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ >; + bootph-all; }; eeprom_wp_pins_default: eeprom-wp-default-pins { @@ -169,6 +178,7 @@ AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -185,6 +195,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; + bootph-all; }; rtc_pins_default: rtc-defaults-pins { @@ -201,26 +212,29 @@ }; &cpsw3g_mdio { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; + bootph-all; + status = "okay"; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&main_gpio0>; interrupts = <84 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; + bootph-all; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; status = "okay"; }; @@ -262,10 +276,11 @@ }; &main_i2c0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; + status = "okay"; eeprom@50 { compatible = "atmel,24c32"; @@ -330,6 +345,10 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, @@ -362,9 +381,9 @@ }; &ospi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; serial_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -377,15 +396,17 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; &sdhci0 { - status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; + bootph-all; + status = "okay"; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index bc8e1ce11047..f63c101b7d61 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -171,6 +171,7 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; @@ -275,6 +276,7 @@ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ >; + bootph-all; }; main_spi0_pins_default: main-spi0-default-pins { @@ -291,6 +293,7 @@ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -349,10 +352,10 @@ }; &main_i2c1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + status = "okay"; eeprom@51 { compatible = "atmel,24c02"; @@ -382,25 +385,25 @@ }; &main_mcan0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&can_tc1>; + status = "okay"; }; &main_mcan1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&can_tc2>; + status = "okay"; }; &main_spi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; ti,pindir-d0-out-d1-in; + status = "okay"; tpm@1 { compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; @@ -410,25 +413,27 @@ }; &main_uart0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; }; &main_uart1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + status = "okay"; }; &sdhci1 { - status = "okay"; vmmc-supply = <&vcc_3v3_mmc>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; + status = "okay"; }; &serdes0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso new file mode 100644 index 000000000000..996c42ec4253 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Authors: + * Wadim Egorov <w.egorov@phytec.de> + * Daniel Schultz <d.schultz@phytec.de> + * + * GPIO, SPI and UART examples for the X27 expansion connector. + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + aliases { + serial5 = "/bus@f4000/serial@2830000"; + }; +}; + +&main_pmx0 { + main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */ + >; + }; + + main_spi1_pins_default: main-spi1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ + AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ + AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */ + AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */ + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */ + >; + }; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_exp_header_gpio_pins_default>; + status = "okay"; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>; + ti,pindir-d0-out-d1-in = <1>; + status = "okay"; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 4c1e02a4e7a2..4421852161dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -540,6 +540,7 @@ #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_USB3>; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 69b3d1ed8a21..440ef57be294 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1040,6 +1040,7 @@ #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_USB3>; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index b3a0385ed3d8..54fc5c4f8c3f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -448,6 +448,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index d184e9c1a0a5..2127316f36a3 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -263,6 +263,13 @@ bootph-all; }; + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -590,7 +597,7 @@ p05-hog { /* P05 - USB2.0_MUX_SEL */ gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; + gpios = <5 GPIO_ACTIVE_LOW>; output-high; }; @@ -631,6 +638,27 @@ }; }; +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + pca9543_0: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 3ac2d45a0558..6850f50530f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -154,6 +154,189 @@ }; }; + ti_csi2rx1: ticsi2rx@30122000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30122000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5100 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30121000 0x00 0x1000>; + clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30142000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + dmas = <&main_bcdma_csi 0 0x5200 0>; + dma-names = "rx0"; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30141000 0x00 0x1000>; + clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30162000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5300 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30161000 0x00 0x1000>; + clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy3>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi3_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi3_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi3_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi3_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30130000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@30150000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30150000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy3: phy@30170000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30170000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_r5fss0: r5fss@78400000 { compatible = "ti,am62-r5fss"; #address-cells = <1>; @@ -204,6 +387,16 @@ }; }; +&main_bcdma_csi { + compatible = "ti,j722s-dmss-bcdma-csi"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + ti,sci-rm-range-tchan = <0x22>; +}; + /* MCU domain overrides */ &mcu_r5fss0_core0 { @@ -251,21 +444,6 @@ ti,interrupt-ranges = <7 71 21>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 17>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso index dcd2c7c39ec3..c1f9573557d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -102,13 +102,6 @@ gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; - - /* Toggle MUX2 for MDIO lines */ - mux-sel-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; - output-high; - }; }; &main_pmx0 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 83bbf94b58d1..1944616ab357 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -84,7 +84,9 @@ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ - <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ + <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, <J784S4_SERDES0_LANE2_IP3_UNUSED>, @@ -193,7 +195,7 @@ ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>, /* GICR */ <0x00 0x6f000000 0x00 0x2000>, /* GICC */ <0x00 0x6f010000 0x00 0x1000>, /* GICH */ diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 1068b0fa8e98..7f5a8801cad1 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -29,3 +29,5 @@ zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv- dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb + +dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi new file mode 100644 index 000000000000..b7a8a1a512cb --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET fixed clock + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/ { + clk60: clk60 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + }; + + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + clk160: clk160 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <160000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk450: clk450 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <450000000>; + }; + + clk1200: clk1200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1200000000>; + }; + + firmware { + versal_net_firmware: versal-net-firmware { + compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; + bootph-all; + method = "smc"; + }; + }; +}; + +&adma0 { + clocks = <&clk450>, <&clk450>; +}; + +&adma1 { + clocks = <&clk450>, <&clk450>; +}; + +&adma2 { + clocks = <&clk450>, <&clk450>; +}; + +&adma3 { + clocks = <&clk450>, <&clk450>; +}; + +&adma4 { + clocks = <&clk450>, <&clk450>; +}; + +&adma5 { + clocks = <&clk450>, <&clk450>; +}; + +&adma6 { + clocks = <&clk450>, <&clk450>; +}; + +&adma7 { + clocks = <&clk450>, <&clk450>; +}; + +&can0 { + clocks = <&clk160>, <&clk160>; +}; + +&can1 { + clocks = <&clk160>, <&clk160>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gpio0 { + clocks = <&clk100>; +}; + +&gpio1 { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&i3c0 { + clocks = <&clk100>; +}; + +&i3c1 { + clocks = <&clk100>; +}; + +&ospi { + clocks = <&clk200>; +}; + +&qspi { + clocks = <&clk300>, <&clk300>; +}; + +&rtc { + /* Nothing */ +}; + +&sdhci0 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&sdhci1 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&serial0 { + clocks = <&clk100>, <&clk100>; +}; + +&serial1 { + clocks = <&clk100>, <&clk100>; +}; + +&spi0 { + clocks = <&clk200>, <&clk200>; +}; + +&spi1 { + clocks = <&clk200>, <&clk200>; +}; + +&ttc0 { + clocks = <&clk150>; +}; + +&usb0 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_0 { + clocks = <&clk60>; +}; + +&usb1 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_1 { + clocks = <&clk60>; +}; + +&wwdt0 { + clocks = <&clk150>; +}; + +&wwdt1 { + clocks = <&clk150>; +}; + +&wwdt2 { + clocks = <&clk150>; +}; + +&wwdt3 { + clocks = <&clk150>; +}; + +&lpd_wwdt0 { + clocks = <&clk150>; +}; + +&lpd_wwdt1 { + clocks = <&clk150>; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts b/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts new file mode 100644 index 000000000000..06b2301f48a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Net VNX board revA + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "versal-net.dtsi" +#include "versal-net-clk.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net"; + model = "Xilinx Versal NET VNX revA"; + dma-coherent; + + memory: memory@0 { + reg = <0 0 0 0x80000000>; + device_type = "memory"; + }; + + memory_hi: memory@800000000 { + reg = <8 0 3 0x80000000>; + device_type = "memory"; + }; + + memory_hi2: memory@50000000000 { + reg = <0x500 0 4 0>; + device_type = "memory"; + }; + + chosen { + bootargs = "console=ttyAMA1,115200n8"; + stdout-path = "serial1:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rsc_tbl_carveout: rproc@bbf14000 { + reg = <0 0xbbf14000 0 0x1000>; + no-map; + }; + rpu0vdev0vring0: rpu0vdev0vring0@bbf15000 { + reg = <0 0xbbf15000 0 0x1000>; + no-map; + }; + rpu0vdev0vring1: rpu0vdev0vring1@bbf16000 { + reg = <0 0xbbf16000 0 0x1000>; + no-map; + }; + rpu0vdev0buffer: rpu0vdev0buffer@bbf17000 { + reg = <0 0xbbf17000 0 0xD000>; + no-map; + }; + reserve_others: reserveothers@0 { + reg = <0 0x0 0 0x1c200000>; + no-map; + }; + pdi_update: pdiupdate@1c200000 { + reg = <0 0x1c200000 0 0x6000000>; + no-map; + }; + reserve_optee_atf: reserveopteeatf@22200000 { + reg = <0 0x22200000 0 0x4100000>; + no-map; + }; + }; +}; + +&gem1 { + status = "okay"; + iommus = <&smmu 0x235>; + phy-handle = <&phy>; + phy-mode = "rmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy: ethernet-phy@4 { + reg = <4>; + }; + }; +}; + +&ospi { + num-cs = <2>; + iommus = <&smmu 0x245>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sdhci1 { + status = "okay"; + iommus = <&smmu 0x243>; + non-removable; + disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; + bus-width = <8>; + no-1-8-v; +}; + +&serial1 { + status = "okay"; +}; + +&smmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi new file mode 100644 index 000000000000..fc9f49e57385 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net"; + model = "Xilinx Versal NET"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu100>; + }; + core2 { + cpu = <&cpu200>; + }; + core3 { + cpu = <&cpu300>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu10000>; + }; + + core1 { + cpu = <&cpu10100>; + }; + + core2 { + cpu = <&cpu10200>; + }; + + core3 { + cpu = <&cpu10300>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu20000>; + }; + + core1 { + cpu = <&cpu20100>; + }; + + core2 { + cpu = <&cpu20200>; + }; + + core3 { + cpu = <&cpu20300>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu30000>; + }; + + core1 { + cpu = <&cpu30100>; + }; + + core2 { + cpu = <&cpu30200>; + }; + + core3 { + cpu = <&cpu30300>; + }; + }; + + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu100: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu200: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu300: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10000: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10100: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10200: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10300: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20000: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20100: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20200: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20300: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30000: cpu@30000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30100: cpu@30100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30200: cpu@30200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30300: cpu@30300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <10000>; + }; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-1066000000 { + opp-hz = /bits/ 64 <1066000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1866000000 { + opp-hz = /bits/ 64 <1866000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1999000000 { + opp-hz = /bits/ 64 <1999000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2050000000 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2100000000 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2200000000 { + opp-hz = /bits/ 64 <2200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &dcc; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc = &rtc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &ospi; + spi1 = &qspi; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + bootph-all; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + fpga: fpga-region { + compatible = "fpga-region"; + fpga-mgr = <&versal_fpga>; + #address-cells = <2>; + #size-cells = <2>; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; + }; + + versal_fpga: versal-fpga { + compatible = "xlnx,versal-fpga"; + }; + + amba: axi { + compatible = "simple-bus"; + bootph-all; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adma0: dma-controller@ebd00000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd00000 0 0x1000>; + interrupts = <0 72 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma1: dma-controller@ebd10000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd10000 0 0x1000>; + interrupts = <0 73 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma2: dma-controller@ebd20000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd20000 0 0x1000>; + interrupts = <0 74 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma3: dma-controller@ebd30000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd30000 0 0x1000>; + interrupts = <0 75 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma4: dma-controller@ebd40000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd40000 0 0x1000>; + interrupts = <0 76 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma5: dma-controller@ebd50000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd50000 0 0x1000>; + interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma6: dma-controller@ebd60000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd60000 0 0x1000>; + interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma7: dma-controller@ebd70000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd70000 0 0x1000>; + interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + can0: can@f1980000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1980000 0 0x6000>; + interrupts = <0 27 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + can1: can@f1990000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1990000 0 0x6000>; + interrupts = <0 28 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + gem0: ethernet@f19e0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19e0000 0 0x1000>; + interrupts = <0 39 4>, <0 39 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gem1: ethernet@f19f0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19f0000 0 0x1000>; + interrupts = <0 41 4>, <0 41 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gic: interrupt-controller@e2000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + reg = <0 0xe2000000 0 0x10000>, + <0 0xe2060000 0 0x200000>; + interrupt-controller; + interrupts = <1 9 4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + its: msi-controller@e2040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0xe2040000 0 0x20000>; + }; + }; + + gpio0: gpio@f19d0000 { + compatible = "xlnx,versal-gpio-1.0"; + status = "disabled"; + reg = <0 0xf19d0000 0 0x1000>; + interrupts = <0 20 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@f1020000 { + compatible = "xlnx,pmc-gpio-1.0"; + status = "disabled"; + reg = <0 0xf1020000 0 0x1000>; + interrupts = <0 180 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c0: i2c@f1940000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1940000 0 0x1000>; + interrupts = <0 21 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@f1950000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1950000 0 0x1000>; + interrupts = <0 22 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i3c0: i3c@f1948000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1948000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 21 4>; + }; + + i3c1: i3c@f1958000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1958000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 22 4>; + }; + + ospi: spi@f1010000 { + compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; + status = "disabled"; + reg = <0 0xf1010000 0 0x10000>, + <0 0xc0000000 0 0x20000000>; + interrupts = <0 182 4>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; /* u-boot specific */ + cdns,trigger-address = <0xc0000000>; + }; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "disabled"; + reg = <0 0xf1030000 0 0x1000>; + interrupts = <0 183 4>; + clock-names = "ref_clk", "pclk"; + }; + + rtc: rtc@f12a0000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0 0xf12a0000 0 0x100>; + interrupts = <0 200 4>, <0 201 4>; + interrupt-names = "alarm", "sec"; + calibration = <0x8000>; + }; + + sdhci0: mmc@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0 0xf1040000 0 0x10000>; + interrupts = <0 184 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + }; + + sdhci1: mmc@f1050000 { + compatible = "xlnx,versal-net-emmc"; + status = "disabled"; + reg = <0 0xf1050000 0 0x10000>; + interrupts = <0 186 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; + }; + + serial0: serial@f1920000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1920000 0 0x1000>; + interrupts = <0 25 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@f1930000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1930000 0 0x1000>; + interrupts = <0 26 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + smmu: iommu@ec000000 { + compatible = "arm,smmu-v3"; + status = "disabled"; + reg = <0 0xec000000 0 0x40000>; + #iommu-cells = <1>; + interrupt-names = "combined"; + interrupts = <0 169 4>; + dma-coherent; + }; + + spi0: spi@f1960000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 23 4>; + reg = <0 0xf1960000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + spi1: spi@f1970000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 24 4>; + reg = <0 0xf1970000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + ttc0: timer@f1dc0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 43 4>, <0 44 4>, <0 45 4>; + timer-width = <32>; + reg = <0x0 0xf1dc0000 0x0 0x1000>; + }; + + ttc1: timer@f1dd0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 46 4>, <0 47 4>, <0 48 4>; + timer-width = <32>; + reg = <0x0 0xf1dd0000 0x0 0x1000>; + }; + + ttc2: timer@f1de0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 49 4>, <0 50 4>, <0 51 4>; + timer-width = <32>; + reg = <0x0 0xf1de0000 0x0 0x1000>; + }; + + ttc3: timer@f1df0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 52 4>, <0 53 4>, <0 54 4>; + timer-width = <32>; + reg = <0x0 0xf1df0000 0x0 0x1000>; + }; + + usb0: usb@f1e00000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0 0xf1e00000 0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_0: usb@f1b00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0 0xf1b00000 0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + usb1: usb@f1e10000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0x0 0xf1e10000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_1: usb@f1c00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xf1c00000 0x0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + wwdt0: watchdog@ecc10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecc10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt1: watchdog@ecd10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecd10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt2: watchdog@ece10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xece10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt3: watchdog@ecf10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecf10000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt0: watchdog@ea420000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea420000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt1: watchdog@ea430000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea430000 0 0x10000>; + timeout-sec = <30>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h new file mode 100644 index 000000000000..0aa17f2a2818 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _XLNX_ZYNQMP_CLK_H +#define _XLNX_ZYNQMP_CLK_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif /* _XLNX_ZYNQMP_CLK_H */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 60d1b1acf9a0..52e122fc7c9e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -8,41 +8,46 @@ * Michal Simek <michal.simek@amd.com> */ -#include <dt-bindings/clock/xlnx-zynqmp-clk.h> +#include "xlnx-zynqmp-clk.h" / { - pss_ref_clk: pss_ref_clk { + pss_ref_clk: pss-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; + clock-output-names = "pss_ref_clk"; }; - video_clk: video_clk { + video_clk: video-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "video_clk"; }; - pss_alt_ref_clk: pss_alt_ref_clk { + pss_alt_ref_clk: pss-alt-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; + clock-output-names = "pss_alt_ref_clk"; }; - gt_crx_ref_clk: gt_crx_ref_clk { + gt_crx_ref_clk: gt-crx-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; + clock-output-names = "gt_crx_ref_clk"; }; - aux_ref_clk: aux_ref_clk { + aux_ref_clk: aux-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "aux_ref_clk"; }; }; diff --git a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts index 23cf26cc3e5f..3514ea78f525 100644 --- a/arch/loongarch/boot/dts/loongson-2k1000-ref.dts +++ b/arch/loongarch/boot/dts/loongson-2k1000-ref.dts @@ -90,11 +90,6 @@ #address-cells = <1>; #size-cells = <0>; - spidev@0 { - compatible = "rohm,dh2228fv"; - spi-max-frequency = <100000000>; - reg = <0>; - }; }; &ehci0 { diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 1069134f2e12..a6dda55a2d1d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -32,8 +32,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi index 8230f06ddf48..36a9860f31da 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -20,8 +20,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 9a56de7b91d6..a57dca891965 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -20,8 +20,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index be596d01ff8d..34645a5f6038 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -73,6 +73,13 @@ }; / { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + thermal-zones { soc-thermal { polling-delay-passive = <1000>; @@ -104,6 +111,28 @@ type = "hot"; }; }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; }; board-thermal { @@ -118,6 +147,13 @@ type = "active"; }; }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index fef2a0e0f7a3..aa8b7fcc125d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -165,6 +165,15 @@ }; }; + pwm: pwm@703000c000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x70 0x3000c000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&clkgen GATE_CLK_APB_PWM>; + clock-names = "apb"; + resets = <&rstgen RST_PWM>; + }; + pllclk: clock-controller@70300100c0 { compatible = "sophgo,sg2042-pll"; reg = <0x70 0x300100c0 0x0 0x40>; diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index ac617319a574..92e13ce1c16d 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts new file mode 100644 index 000000000000..448319214104 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> + * Copyright (C) 2025 Javier Martinez Canillas <javierm@redhat.com> + */ + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "Milk-V Jupiter (K1)"; + compatible = "milkv,jupiter", "spacemit,k1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 48fb5091b817..c2f70f5e2918 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -233,7 +233,7 @@ regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1540000>; - regulator-name = "vdd-cpu"; + regulator-name = "vdd_cpu"; }; emmc_vdd: aldo4 { @@ -350,12 +350,6 @@ &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - - spi_dev0: spi@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <10000000>; - }; }; &syscrg { diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts index 30b0715196b6..8d9ce8b69a71 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -11,6 +11,40 @@ compatible = "deepcomputing,fml13v01", "starfive,jh7110"; }; +&pcie1 { + perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&sysgpio { + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = <GPIOMUX(29, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(28, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + &usb0 { dr_mode = "host"; status = "okay"; diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts index b764d4d92fd9..31e825be2065 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -100,3 +100,8 @@ pinctrl-0 = <&usb0_pins>; status = "okay"; }; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index a7aed4a21b65..0ba74ef04679 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -611,6 +611,8 @@ pciephy0: phy@10210000 { compatible = "starfive,jh7110-pcie-phy"; reg = <0x0 0x10210000 0x0 0x10000>; + starfive,sys-syscon = <&sys_syscon 0x18>; + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; #phy-cells = <0>; }; diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..55a448f5ed6d --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 25aed298ac2c..f576e61bec70 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -589,4 +589,9 @@ #define PCLK_EDP_S 569 #define ACLK_KLAD 570 +/* SCMI clocks, use these when changing clocks through SCMI */ +#define SCMI_ARMCLK_L 10 +#define SCMI_ARMCLK_B 11 +#define SCMI_CLK_GPU 456 + #endif diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f3ed..6b9df09d2822 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,25 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 +#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 +#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 +#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 +#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 +#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 +#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 +#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 +#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 +#define CLK_GOUT_PERIS_GIC_CLK 12 +#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 +#define CLK_GOUT_PERIS_MCT_PCLK 14 +#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 +#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 +#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 +#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 + #endif diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cdc4c0b9a374..f0f7ddd3dcbd 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..6b024c5f2e1c --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_NL2 8 +#define SRST_CORE_BIU 9 +#define SRST_CORE_CRYPTO 10 +#define SRST_P_DBG 11 +#define SRST_POT_DBG 12 +#define SRST_NT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_P_DAPLITE_BIU 15 +#define SRST_P_CPU_BIU 16 +#define SRST_REF_PVTPLL_CORE 17 +#define SRST_A_BUS_VOPGL_BIU 18 +#define SRST_A_BUS_H_BIU 19 +#define SRST_A_SYSMEM_BIU 20 +#define SRST_A_BUS_BIU 21 +#define SRST_H_BUS_BIU 22 +#define SRST_P_BUS_BIU 23 +#define SRST_P_DFT2APB 24 +#define SRST_P_BUS_GRF 25 +#define SRST_A_BUS_M_BIU 26 +#define SRST_A_GIC 27 +#define SRST_A_SPINLOCK 28 +#define SRST_A_DMAC 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_P_JDBCK_DAP 37 +#define SRST_JDBCK_DAP 38 +#define SRST_P_WDT_NS 39 +#define SRST_T_WDT_NS 40 +#define SRST_H_TRNG_NS 41 +#define SRST_P_UART0 42 +#define SRST_S_UART0 43 +#define SRST_PKA_CRYPTO 44 +#define SRST_A_CRYPTO 45 +#define SRST_H_CRYPTO 46 +#define SRST_P_DMA2DDR 47 +#define SRST_A_DMA2DDR 48 +#define SRST_P_PWM0 49 +#define SRST_PWM0 50 +#define SRST_P_PWM1 51 +#define SRST_PWM1 52 +#define SRST_P_SCR 53 +#define SRST_A_DCF 54 +#define SRST_P_INTMUX 55 +#define SRST_A_VPU_BIU 56 +#define SRST_H_VPU_BIU 57 +#define SRST_P_VPU_BIU 58 +#define SRST_A_VPU 59 +#define SRST_H_VPU 60 +#define SRST_P_CRU_PCIE 61 +#define SRST_P_VPU_GRF 62 +#define SRST_H_SFC 63 +#define SRST_S_SFC 64 +#define SRST_C_EMMC 65 +#define SRST_H_EMMC 66 +#define SRST_A_EMMC 67 +#define SRST_B_EMMC 68 +#define SRST_T_EMMC 69 +#define SRST_P_GPIO1 70 +#define SRST_DB_GPIO1 71 +#define SRST_A_VPU_L_BIU 72 +#define SRST_P_VPU_IOC 73 +#define SRST_H_SAI_I2S0 74 +#define SRST_M_SAI_I2S0 75 +#define SRST_H_SAI_I2S2 76 +#define SRST_M_SAI_I2S2 77 +#define SRST_P_ACODEC 78 +#define SRST_P_GPIO3 79 +#define SRST_DB_GPIO3 80 +#define SRST_P_SPI1 81 +#define SRST_SPI1 82 +#define SRST_P_UART2 83 +#define SRST_S_UART2 84 +#define SRST_P_UART5 85 +#define SRST_S_UART5 86 +#define SRST_P_UART6 87 +#define SRST_S_UART6 88 +#define SRST_P_UART7 89 +#define SRST_S_UART7 90 +#define SRST_P_I2C3 91 +#define SRST_I2C3 92 +#define SRST_P_I2C5 93 +#define SRST_I2C5 94 +#define SRST_P_I2C6 95 +#define SRST_I2C6 96 +#define SRST_A_MAC 97 +#define SRST_P_PCIE 98 +#define SRST_PCIE_PIPE_PHY 99 +#define SRST_PCIE_POWER_UP 100 +#define SRST_P_PCIE_PHY 101 +#define SRST_P_PIPE_GRF 102 +#define SRST_H_SDIO0 103 +#define SRST_H_SDIO1 104 +#define SRST_TS_0 105 +#define SRST_TS_1 106 +#define SRST_P_CAN2 107 +#define SRST_CAN2 108 +#define SRST_P_CAN3 109 +#define SRST_CAN3 110 +#define SRST_P_SARADC 111 +#define SRST_SARADC 112 +#define SRST_SARADC_PHY 113 +#define SRST_P_TSADC 114 +#define SRST_TSADC 115 +#define SRST_A_USB3OTG 116 +#define SRST_A_GPU_BIU 117 +#define SRST_P_GPU_BIU 118 +#define SRST_A_GPU 119 +#define SRST_REF_PVTPLL_GPU 120 +#define SRST_H_RKVENC_BIU 121 +#define SRST_A_RKVENC_BIU 122 +#define SRST_P_RKVENC_BIU 123 +#define SRST_H_RKVENC 124 +#define SRST_A_RKVENC 125 +#define SRST_CORE_RKVENC 126 +#define SRST_H_SAI_I2S1 127 +#define SRST_M_SAI_I2S1 128 +#define SRST_P_I2C1 129 +#define SRST_I2C1 130 +#define SRST_P_I2C0 131 +#define SRST_I2C0 132 +#define SRST_P_SPI0 133 +#define SRST_SPI0 134 +#define SRST_P_GPIO4 135 +#define SRST_DB_GPIO4 136 +#define SRST_P_RKVENC_IOC 137 +#define SRST_H_SPDIF 138 +#define SRST_M_SPDIF 139 +#define SRST_H_PDM 140 +#define SRST_M_PDM 141 +#define SRST_P_UART1 142 +#define SRST_S_UART1 143 +#define SRST_P_UART3 144 +#define SRST_S_UART3 145 +#define SRST_P_RKVENC_GRF 146 +#define SRST_P_CAN0 147 +#define SRST_CAN0 148 +#define SRST_P_CAN1 149 +#define SRST_CAN1 150 +#define SRST_A_VO_BIU 151 +#define SRST_H_VO_BIU 152 +#define SRST_P_VO_BIU 153 +#define SRST_H_RGA2E 154 +#define SRST_A_RGA2E 155 +#define SRST_CORE_RGA2E 156 +#define SRST_H_VDPP 157 +#define SRST_A_VDPP 158 +#define SRST_CORE_VDPP 159 +#define SRST_P_VO_GRF 160 +#define SRST_P_CRU 161 +#define SRST_A_VOP_BIU 162 +#define SRST_H_VOP 163 +#define SRST_D_VOP0 164 +#define SRST_D_VOP1 165 +#define SRST_A_VOP 166 +#define SRST_P_HDMI 167 +#define SRST_HDMI 168 +#define SRST_P_HDMIPHY 169 +#define SRST_H_HDCP_KEY 170 +#define SRST_A_HDCP 171 +#define SRST_H_HDCP 172 +#define SRST_P_HDCP 173 +#define SRST_H_CVBS 174 +#define SRST_D_CVBS_VOP 175 +#define SRST_D_4X_CVBS_VOP 176 +#define SRST_A_JPEG_DECODER 177 +#define SRST_H_JPEG_DECODER 178 +#define SRST_A_VO_L_BIU 179 +#define SRST_A_MAC_VO 180 +#define SRST_A_JPEG_BIU 181 +#define SRST_H_SAI_I2S3 182 +#define SRST_M_SAI_I2S3 183 +#define SRST_MACPHY 184 +#define SRST_P_VCDCPHY 185 +#define SRST_P_GPIO2 186 +#define SRST_DB_GPIO2 187 +#define SRST_P_VO_IOC 188 +#define SRST_H_SDMMC0 189 +#define SRST_P_OTPC_NS 190 +#define SRST_SBPI_OTPC_NS 191 +#define SRST_USER_OTPC_NS 192 +#define SRST_HDMIHDP0 193 +#define SRST_H_USBHOST 194 +#define SRST_H_USBHOST_ARB 195 +#define SRST_HOST_UTMI 196 +#define SRST_P_UART4 197 +#define SRST_S_UART4 198 +#define SRST_P_I2C4 199 +#define SRST_I2C4 200 +#define SRST_P_I2C7 201 +#define SRST_I2C7 202 +#define SRST_P_USBPHY 203 +#define SRST_USBPHY_POR 204 +#define SRST_USBPHY_OTG 205 +#define SRST_USBPHY_HOST 206 +#define SRST_P_DDRPHY_CRU 207 +#define SRST_H_RKVDEC_BIU 208 +#define SRST_A_RKVDEC_BIU 209 +#define SRST_A_RKVDEC 210 +#define SRST_H_RKVDEC 211 +#define SRST_HEVC_CA_RKVDEC 212 +#define SRST_REF_PVTPLL_RKVDEC 213 +#define SRST_P_DDR_BIU 214 +#define SRST_P_DDRC 215 +#define SRST_P_DDRMON 216 +#define SRST_TIMER_DDRMON 217 +#define SRST_P_MSCH_BIU 218 +#define SRST_P_DDR_GRF 219 +#define SRST_P_DDR_HWLP 220 +#define SRST_P_DDRPHY 221 +#define SRST_MSCH_BIU 222 +#define SRST_A_DDR_UPCTL 223 +#define SRST_DDR_UPCTL 224 +#define SRST_DDRMON 225 +#define SRST_A_DDR_SCRAMBLE 226 +#define SRST_A_SPLIT 227 +#define SRST_DDR_PHY 228 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h index a01af169d249..b46de214dd09 100644 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -9,9 +9,18 @@ #ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H #define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H -#define USI_V2_NONE 0 -#define USI_V2_UART 1 -#define USI_V2_SPI 2 -#define USI_V2_I2C 3 +#define USI_MODE_NONE 0 +#define USI_MODE_UART 1 +#define USI_MODE_SPI 2 +#define USI_MODE_I2C 3 +#define USI_MODE_I2C1 4 +#define USI_MODE_I2C0_1 5 +#define USI_MODE_UART_I2C1 6 + +/* Deprecated */ +#define USI_V2_NONE USI_MODE_NONE +#define USI_V2_UART USI_MODE_UART +#define USI_V2_SPI USI_MODE_SPI +#define USI_V2_I2C USI_MODE_I2C #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ |