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author | 2017-02-19 22:41:42 +0100 | |
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committer | 2017-03-06 09:55:53 -0800 | |
commit | 2f739c17507e339edd8cfad1c1af5580e261a853 (patch) | |
tree | e2deca9ffa58c992d1ddfe8b098ab7b2a55479fd | |
parent | ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO (diff) | |
download | wireguard-linux-2f739c17507e339edd8cfad1c1af5580e261a853.tar.xz wireguard-linux-2f739c17507e339edd8cfad1c1af5580e261a853.zip |
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
This resets the ethernet PHY during boot to get the PHY into a "clean"
state.
While here also specify the phy-handle of the ethmac node to make the
PHY configuration similar to the one we have on GXL devices. This will
allow us to specify OF-properties for the PHY itself.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
-rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index fc0e86cb4cde..acb035d119d7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -96,6 +96,29 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@3 { + /* Micrel KSZ9031 (0x00221620) */ + reg = <3>; + }; + }; +}; + &i2c_B { status = "okay"; pinctrl-0 = <&i2c_b_pins>; |