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author | 2024-09-10 06:35:11 +0800 | |
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committer | 2024-10-04 13:06:51 +0800 | |
commit | 30003e3f802ec4e353cecae3fc2a4c3cd25b63fe (patch) | |
tree | dfab226cd136fae4a8a6749ea5174d25ebe227d8 | |
parent | riscv: dts: sophgo: cv1800b: add pinctrl support (diff) | |
download | wireguard-linux-30003e3f802ec4e353cecae3fc2a4c3cd25b63fe.tar.xz wireguard-linux-30003e3f802ec4e353cecae3fc2a4c3cd25b63fe.zip |
riscv: dts: sophgo: cv1812h: add pinctrl support
Add pinctrl node for CV1812H SoC.
Link: https://lore.kernel.org/r/IA1PR20MB49533DB3D0C1861938185015BB992@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
-rw-r--r-- | arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi index 7fa4c1e2d1da..815114db54ed 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/pinctrl-cv1812h.h> #include "cv18xx.dtsi" / { @@ -13,6 +14,15 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; }; + + soc { + pinctrl: pinctrl@3001000 { + compatible = "sophgo,cv1812h-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; }; &plic { |