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| author |   Arnd Bergmann <arnd@arndb.de> | 2022-05-13 11:32:42 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-05-13 11:32:42 +0200 |
| commit | 30258ae65a06b0128d4020992a8d851cdef7c207 (patch) | |
| tree | e286c850a13ba11f230294fc9564915e1d715deb | |
| parent | Merge tag 'hisi-armv7soc-for-5.19' of https://github.com/hisilicon/linux-hisi into arm/soc (diff) | |
| parent | ARM: rockchip: fix typos in comments (diff) | |
| download | wireguard-linux-30258ae65a06b0128d4020992a8d851cdef7c207.tar.xz wireguard-linux-30258ae65a06b0128d4020992a8d851cdef7c207.zip | |
Merge tag 'v5.19-rockchip-soc32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/soc
Comment typo fix.
* tag 'v5.19-rockchip-soc32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: fix typos in comments
Link: https://lore.kernel.org/r/4421093.ElGaqSPkdT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/mach-rockchip/platsmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5ec58d004b7d..36915a073c23 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -137,7 +137,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) /* * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will - * stay at wfe state, once they are actived, they will check + * stay at wfe state, once they are activated, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc |