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authorMatthew Auld <matthew.auld@intel.com>2020-11-09 11:12:49 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2020-11-09 13:38:41 +0000
commit330b7d33056bb0fa7d7f672d4a98495f200fe9d4 (patch)
treec67a8f83e20bcd070ff2d59a4fca43fbd8668427
parentdrm/i915: Use ABI engine class in error state ecode (diff)
downloadwireguard-linux-330b7d33056bb0fa7d7f672d4a98495f200fe9d4.tar.xz
wireguard-linux-330b7d33056bb0fa7d7f672d4a98495f200fe9d4.zip
drm/i915/region: fix order when adding blocks
When performing an allocation we try split it down into the largest possible power-of-two blocks/pages-sizes, and for the common case we expect to allocate the blocks in descending order. This also naturally fits with our GTT alignment tricks(including the hugepages selftest), where we sometimes try to align to the largest possible GTT page-size for the allocation, in the hope that translates to bigger GTT page-sizes. Currently, we seem to incorrectly add the blocks in the opposite order, which is definitely not the intended behaviour. Reported-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: CQ Tang <cq.tang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20201109111249.109365-1-matthew.auld@intel.com
-rw-r--r--drivers/gpu/drm/i915/intel_memory_region.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 180e1078ef7c..b326993a1026 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -114,7 +114,7 @@ __intel_memory_region_get_pages_buddy(struct intel_memory_region *mem,
n_pages -= BIT(order);
block->private = mem;
- list_add(&block->link, blocks);
+ list_add_tail(&block->link, blocks);
if (!n_pages)
break;