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| author |   Vincenzo Frascino <vincenzo.frascino@arm.com> | 2025-02-21 18:03:48 +0000 |
|---|---|---|
| committer |   Sudeep Holla <sudeep.holla@arm.com> | 2025-02-27 11:13:14 +0000 |
| commit | 34f3b3745ce5850c5ea3f8cb80449a65e60be54b (patch) | |
| tree | 5381240be34d1f3bfd162a3ea6585eee847276ea | |
| parent | arm64: dts: morello: Add support for soc dts (diff) | |
| download | wireguard-linux-34f3b3745ce5850c5ea3f8cb80449a65e60be54b.tar.xz wireguard-linux-34f3b3745ce5850c5ea3f8cb80449a65e60be54b.zip | |
arm64: dts: morello: Add support for fvp dts
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
Introduce Morello fvp dts.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/arm/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/arm/morello-fvp.dts | 77 |
2 files changed, 78 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello Fixed Virtual Platform"; + compatible = "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + }; + + net_0: virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + + rng_0: virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + kmi_0: kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&uart0 { + status = "okay"; +}; |