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authorNaman Trivedi <naman.trivedimanojbhai@amd.com>2024-11-22 01:57:12 -0800
committerMichal Simek <michal.simek@amd.com>2025-02-03 17:12:39 +0100
commit385a59e7f7fb3438466a0712cc14672c708bbd57 (patch)
tree7e243ac4ba3a13dcc48eeab696501f84bc843f62
parentLinux 6.14-rc1 (diff)
downloadwireguard-linux-385a59e7f7fb3438466a0712cc14672c708bbd57.tar.xz
wireguard-linux-385a59e7f7fb3438466a0712cc14672c708bbd57.zip
arm64: zynqmp: add clock-output-names property in clock nodes
Add clock-output-names property to clock nodes, so that the resulting clock name do not change when clock node name is changed. Also, replace underscores with hyphens in the clock node names as per dt-schema rule. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com> Link: https://lore.kernel.org/r/20241122095712.1166883-1-naman.trivedimanojbhai@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi15
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 60d1b1acf9a0..385fed8a852a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -10,39 +10,44 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
- pss_ref_clk: pss_ref_clk {
+ pss_ref_clk: pss-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
+ clock-output-names = "pss_ref_clk";
};
- video_clk: video_clk {
+ video_clk: video-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
+ clock-output-names = "video_clk";
};
- pss_alt_ref_clk: pss_alt_ref_clk {
+ pss_alt_ref_clk: pss-alt-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
+ clock-output-names = "pss_alt_ref_clk";
};
- gt_crx_ref_clk: gt_crx_ref_clk {
+ gt_crx_ref_clk: gt-crx-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
+ clock-output-names = "gt_crx_ref_clk";
};
- aux_ref_clk: aux_ref_clk {
+ aux_ref_clk: aux-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
+ clock-output-names = "aux_ref_clk";
};
};