diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-30 18:34:42 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-05-05 21:12:57 +0300 |
| commit | 3b71a9b6cffd0aaa0fe2fb0e38ba068cab319c77 (patch) | |
| tree | 48d3d1af3ed85efcc470a3fd54770b603b5eb934 | |
| parent | drm/i915: Use intel_de_rmw() in bdw cdclk programming (diff) | |
| download | wireguard-linux-3b71a9b6cffd0aaa0fe2fb0e38ba068cab319c77.tar.xz wireguard-linux-3b71a9b6cffd0aaa0fe2fb0e38ba068cab319c77.zip | |
drm/i915: Use intel_de_rmw() in skl cdclk programming
Replace the hand rolled rmw sequences with intel_de_rmw().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210430153444.29270-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 024620520746..45c4070910dc 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -970,20 +970,16 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { - u32 val; - - val = intel_de_read(dev_priv, DPLL_CTRL1); - - val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | - DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); - val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); - val |= skl_dpll0_link_rate(dev_priv, vco); - - intel_de_write(dev_priv, DPLL_CTRL1, val); + intel_de_rmw(dev_priv, DPLL_CTRL1, + DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | + DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), + DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | + skl_dpll0_link_rate(dev_priv, vco)); intel_de_posting_read(dev_priv, DPLL_CTRL1); - intel_de_write(dev_priv, LCPLL1_CTL, - intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE); + intel_de_rmw(dev_priv, LCPLL1_CTL, + 0, LCPLL_PLL_ENABLE); if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) drm_err(&dev_priv->drm, "DPLL0 not locked\n"); @@ -996,8 +992,9 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) static void skl_dpll0_disable(struct drm_i915_private *dev_priv) { - intel_de_write(dev_priv, LCPLL1_CTL, - intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); + intel_de_rmw(dev_priv, LCPLL1_CTL, + LCPLL_PLL_ENABLE, 0); + if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); |