diff options
| author |   Dillon Varone <dillon.varone@amd.com> | 2022-04-14 17:03:28 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:44:33 -0400 |
| commit | 3ccb9ea9976022034d8fffd8d929d6e70a24e0c6 (patch) | |
| tree | 0239b32e2dc45890a2e300ed0f123bb9ac390818 | |
| parent | drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7 (diff) | |
| download | wireguard-linux-3ccb9ea9976022034d8fffd8d929d6e70a24e0c6.tar.xz wireguard-linux-3ccb9ea9976022034d8fffd8d929d6e70a24e0c6.zip | |
drm/amd/display: Add additional guard for FCLK pstate message for DCN321
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 93fbecbc8065..9d2d2cda5543 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -346,8 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } - if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && - clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) { + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && + should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) { clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; /* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */ @@ -368,7 +368,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); - if (clk_mgr_base->clks.fclk_p_state_change_support && + if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && + clk_mgr_base->clks.fclk_p_state_change_support && (update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) { /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); |