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| author |   Chen Wang <unicorn_wang@outlook.com> | 2024-08-05 10:33:20 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2024-08-19 18:02:08 +0100 |
| commit | 3ccedd259cc3e78666514881b37466a8b977b0d8 (patch) | |
| tree | 871c7ff9516bef06feacc6070c2c1b6510347c43 | |
| parent | Linux 6.11-rc1 (diff) | |
| download | wireguard-linux-3ccedd259cc3e78666514881b37466a8b977b0d8.tar.xz wireguard-linux-3ccedd259cc3e78666514881b37466a8b977b0d8.zip | |
riscv: defconfig: sophgo: enable clks for sg2042
Enable clk generators for sg2042 due to many peripherals rely on
these clocks.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/configs/defconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 0d678325444f..d43a028909e5 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -249,6 +249,9 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_CLK_SOPHGO_CV1800=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y CONFIG_SUN8I_DE2_CCU=m CONFIG_RENESAS_OSTM=y CONFIG_SUN50I_IOMMU=y |