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| author |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-07-04 11:26:03 -0300 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-10 22:09:37 +0200 |
| commit | 3fcf305b36a7be8bfc8f9e53b0498fbba7768da6 (patch) | |
| tree | e789ef1e8148ad9a75e5a9c817dbe6a9cd9d1b14 | |
| parent | drm/i915: State readout and cross-checking for ddi_pll_sel (diff) | |
| download | wireguard-linux-3fcf305b36a7be8bfc8f9e53b0498fbba7768da6.tar.xz wireguard-linux-3fcf305b36a7be8bfc8f9e53b0498fbba7768da6.zip | |
drm/i915: BDW also has special-purpose DP DDI clocks
Don't let it fall in the HAS_PCH_SPLIT() case.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3ca6c7c77e05..568e532e3b42 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -756,7 +756,7 @@ intel_dp_set_clock(struct intel_encoder *encoder, if (IS_G4X(dev)) { divisor = gen4_dpll; count = ARRAY_SIZE(gen4_dpll); - } else if (IS_HASWELL(dev)) { + } else if (HAS_DDI(dev)) { /* Haswell has special-purpose DP DDI clocks. */ } else if (HAS_PCH_SPLIT(dev)) { divisor = pch_dpll; |