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| author |   Andy Yan <andy.yan@rock-chips.com> | 2025-03-03 11:44:19 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-03-03 22:35:23 +0100 |
| commit | 47d31e6598e4fda1433e747ef031cb972c57c5ae (patch) | |
| tree | 40ffd306a6a0cc0ac4dbd679b0ef731b8da98fed | |
| parent | dt-bindings: display: vop2: describe constraint SoC by SoC (diff) | |
| download | wireguard-linux-47d31e6598e4fda1433e747ef031cb972c57c5ae.tar.xz wireguard-linux-47d31e6598e4fda1433e747ef031cb972c57c5ae.zip | |
dt-bindings: display: vop2: Add missing rockchip,grf property for rk3566/8
The clock polarity of RGB signal output is controlled by GRF, this
property is already being used in the current device tree, but
forgot to describe it as a required property in the binding file.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20250303034436.192400-6-andyshrk@163.com
| -rw-r--r-- | Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml index a5771edd83b5..083eadcf0588 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -146,6 +146,9 @@ allOf: rockchip,vop-grf: false rockchip,pmu: false + required: + - rockchip,grf + - if: properties: compatible: @@ -200,6 +203,7 @@ examples: "dclk_vp1", "dclk_vp2"; power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; iommus = <&vop_mmu>; vop_out: ports { #address-cells = <1>; |