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author | 2015-06-02 18:35:39 +0000 | |
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committer | 2015-06-02 14:19:27 -0500 | |
commit | 4c060b89c1af20b3a9d6393072ac85b4a3ccc300 (patch) | |
tree | ebc8a658ceae35bd68a738a23f8655df0ddda46c | |
parent | ARM: socfpga: dts: add enable-method property for cpu nodes (diff) | |
download | wireguard-linux-4c060b89c1af20b3a9d6393072ac85b4a3ccc300.tar.xz wireguard-linux-4c060b89c1af20b3a9d6393072ac85b4a3ccc300.zip |
ARM: socfpga: dts: add sdram controller dt binding doc
Add binding doc for Altera SOCFPGA SDRAM controller.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
-rw-r--r-- | Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt new file mode 100644 index 000000000000..77ca635765e1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Controller + +Required properties: +- compatible : Should contain "altr,sdr-ctl" and "syscon". + syscon is required by the Altera SOCFPGA SDRAM EDAC. +- reg : Should contain 1 register range (address and length) + +Example: + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; |