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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 16:46:36 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-04-21 12:31:42 -0500 |
| commit | 52358c64937e982d3cdcf64be58f08f30d8e518c (patch) | |
| tree | cf38a6a4f3900d8fc2e271bde4fa4ccd2f1267de | |
| parent | arm64: dts: qcom: ipq8074: Add PCIe bridge node (diff) | |
| download | wireguard-linux-52358c64937e982d3cdcf64be58f08f30d8e518c.tar.xz wireguard-linux-52358c64937e982d3cdcf64be58f08f30d8e518c.zip | |
arm64: dts: qcom: ipq6018: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; |