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| author |   Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-14 15:55:45 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-23 17:24:20 +0000 |
| commit | 5637a126482026b37d426d76e1b18f748f309aaa (patch) | |
| tree | 1c96bfd035394dc2c4de0376571a1d34d47a49a4 | |
| parent | ARM: 6663/1: make Thumb2 kernel entry point more similar to the ARM one (diff) | |
| download | wireguard-linux-5637a126482026b37d426d76e1b18f748f309aaa.tar.xz wireguard-linux-5637a126482026b37d426d76e1b18f748f309aaa.zip | |
ARM: move L1_CACHE_SHIFT_6 to mm/Kconfig
Move L1_CACHE_SHIFT related options together, rather than spreading them
across two separate Kconfig files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/mm/Kconfig | 5 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5cff165b7eb0..65ea7bb57c4d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -178,11 +178,6 @@ config FIQ config ARCH_MTD_XIP bool -config ARM_L1_CACHE_SHIFT_6 - bool - help - Setting ARM L1 cache line size to 64 Bytes. - config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9d30c6f804b9..a51661be1412 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -845,6 +845,11 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. +config ARM_L1_CACHE_SHIFT_6 + bool + help + Setting ARM L1 cache line size to 64 Bytes. + config ARM_L1_CACHE_SHIFT int default 6 if ARM_L1_CACHE_SHIFT_6 |