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| author |   Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2024-10-14 10:54:18 -0700 |
|---|---|---|
| committer |   Drew Fustini <dfustini@tenstorrent.com> | 2024-10-15 10:01:17 -0700 |
| commit | 566ab427f827b0256d3e8ce0235d088e6a9c28bd (patch) | |
| tree | 5b88b83bb1cc4c4e2f86a238a1ee8690ba1604b6 | |
| parent | Linux 6.12-rc3 (diff) | |
| download | wireguard-linux-566ab427f827b0256d3e8ce0235d088e6a9c28bd.tar.xz wireguard-linux-566ab427f827b0256d3e8ce0235d088e6a9c28bd.zip | |
riscv: dts: thead: Add TH1520 pin control nodes
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC.
Add the missing aonsys_clk for the always-on pin controller as there is
not yet an aon subsys clock controller driver.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: modify description as there is now an ap_subsys clk driver]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
| -rw-r--r-- | arch/riscv/boot/dts/thead/th1520.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 6992060e6a54..93c17f52fbe9 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -216,6 +216,13 @@ #clock-cells = <0>; }; + aonsys_clk: clock-73728000 { + compatible = "fixed-clock"; + clock-frequency = <73728000>; + clock-output-names = "aonsys_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -354,6 +361,13 @@ }; }; + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL1>; + thead,pad-group = <2>; + }; + gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; @@ -392,6 +406,13 @@ }; }; + padctrl0_apsys: pinctrl@ffec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL0>; + thead,pad-group = <3>; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -538,6 +559,13 @@ }; }; + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + clocks = <&aonsys_clk>; + thead,pad-group = <1>; + }; + ao_gpio1: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; |