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authorShubhrajyoti Datta <shubhrajyoti.datta@amd.com>2025-02-04 09:30:32 +0100
committerMichal Simek <michal.simek@amd.com>2025-02-17 15:22:53 +0100
commit573debf03034b15a01e424afd1d06faa1014f7d3 (patch)
tree6461c7c3beb0e2bb8fb9720a1b0b76639a8fec61
parentarm64: zynqmp: add clock-output-names property in clock nodes (diff)
downloadwireguard-linux-573debf03034b15a01e424afd1d06faa1014f7d3.tar.xz
wireguard-linux-573debf03034b15a01e424afd1d06faa1014f7d3.zip
dt-bindings: soc: Add new VN-X board description based on Versal NET
The Versal NET (Networked Adaptive Compute Acceleration Platform) from AMD/Xilinx is a next-generation adaptive platform designed for high performance computing, networking, and AI acceleration. It is part of the Versal ACAP (Adaptive Compute Acceleration Platform) family. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e4486141cf9b1d36b03624cc73621b2e3bba894.1738657826.git.michal.simek@amd.com
-rw-r--r--Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml11
1 files changed, 9 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index 131aba5ed9f4..fb5c39c79d28 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@amd.com>
-description: |
- Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
+description:
+ AMD/Xilinx boards with ARM 32/64bits cores
properties:
$nodename:
@@ -187,6 +187,13 @@ properties:
- const: qemu,mbv
- const: amd,mbv
+ - description: Xilinx Versal NET VN-X revA platform
+ items:
+ enum:
+ - xlnx,versal-net-vnx-revA
+ - xlnx,versal-net-vnx
+ - xlnx,versal-net
+
additionalProperties: true
...