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authorBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:14:51 -0500
committerBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:14:51 -0500
commit6547faa1bc25c4392473b80615cc30088295c89c (patch)
treead28477054e51a71f3f4972f91dec53b2f40aee0
parentMerge branch 'pci/controller/mediatek' (diff)
parentPCI: qcom-ep: Enable EP mode support for SAR2130P (diff)
downloadwireguard-linux-6547faa1bc25c4392473b80615cc30088295c89c.tar.xz
wireguard-linux-6547faa1bc25c4392473b80615cc30088295c89c.zip
Merge branch 'pci/controller/qcom'
- Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as RESERVED (Manivannan Sadhasivam) - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry Baryshkov) - Make DT iommu property required for SA8775P and prohibited for SDX55 (Dmitry Baryshkov) - Add DT iommu and DMA-related properties for Qualcomm SM8450 (Dmitry Baryshkov) - Consolidate DMA vs non-DMA cases in DT (Dmitry Baryshkov) - Add endpoint DT properties for SAR2130P and enable endpoint mode in driver (Dmitry Baryshkov) * pci/controller/qcom: PCI: qcom-ep: Enable EP mode support for SAR2130P dt-bindings: PCI: qcom-ep: Add SAR2130P compatible dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases dt-bindings: PCI: qcom-ep: Enable DMA for SM8450 dt-bindings: PCI: qcom-ep: Describe optional IOMMU dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml100
-rw-r--r--drivers/pci/controller/dwc/pcie-qcom-ep.c5
2 files changed, 79 insertions, 26 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 1226ee5d08d1..ac3414203d38 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -14,6 +14,7 @@ properties:
oneOf:
- enum:
- qcom,sa8775p-pcie-ep
+ - qcom,sar2130p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
@@ -44,11 +45,11 @@ properties:
clocks:
minItems: 5
- maxItems: 8
+ maxItems: 9
clock-names:
minItems: 5
- maxItems: 8
+ maxItems: 9
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@@ -75,6 +76,9 @@ properties:
- const: doorbell
- const: dma
+ iommus:
+ maxItems: 1
+
reset-gpios:
description: GPIO used as PERST# input signal
maxItems: 1
@@ -91,6 +95,8 @@ properties:
- const: pcie-mem
- const: cpu-pcie
+ dma-coherent: true
+
resets:
maxItems: 1
@@ -126,6 +132,38 @@ required:
allOf:
- $ref: pci-ep.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sar2130p-pcie-ep
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ - description: PCIe DDRSS SF TBU clock
+ - description: PCIe AGGRE NOC AXI clock
+ - description: PCIe CFG NOC AXI clock
+ - description: PCIe QMIP AHB clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ - const: ddrss_sf_tbu
+ - const: aggre_noc_axi
+ - const: cnoc_sf_axi
+ - const: qmip_pcie_ahb
+
- if:
properties:
compatible:
@@ -135,9 +173,43 @@ allOf:
then:
properties:
reg:
+ minItems: 6
maxItems: 6
reg-names:
+ minItems: 6
maxItems: 6
+ interrupts:
+ minItems: 2
+ maxItems: 2
+ interrupt-names:
+ minItems: 2
+ maxItems: 2
+ iommus: false
+ else:
+ properties:
+ reg:
+ minItems: 7
+ maxItems: 7
+ reg-names:
+ minItems: 7
+ maxItems: 7
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
+ required:
+ - iommus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx55-pcie-ep
+ then:
+ properties:
clocks:
items:
- description: PCIe Auxiliary clock
@@ -156,10 +228,6 @@ allOf:
- const: slave_q2a
- const: sleep
- const: ref
- interrupts:
- maxItems: 2
- interrupt-names:
- maxItems: 2
- if:
properties:
@@ -169,10 +237,6 @@ allOf:
- qcom,sm8450-pcie-ep
then:
properties:
- reg:
- maxItems: 6
- reg-names:
- maxItems: 6
clocks:
items:
- description: PCIe Auxiliary clock
@@ -193,10 +257,6 @@ allOf:
- const: ref
- const: ddrss_sf_tbu
- const: aggre_noc_axi
- interrupts:
- maxItems: 2
- interrupt-names:
- maxItems: 2
- if:
properties:
@@ -206,12 +266,6 @@ allOf:
- qcom,sa8775p-pcie-ep
then:
properties:
- reg:
- minItems: 7
- maxItems: 7
- reg-names:
- minItems: 7
- maxItems: 7
clocks:
items:
- description: PCIe Auxiliary clock
@@ -226,12 +280,6 @@ allOf:
- const: bus_master
- const: bus_slave
- const: slave_q2a
- interrupts:
- minItems: 3
- maxItems: 3
- interrupt-names:
- minItems: 3
- maxItems: 3
unevaluatedProperties: false
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index c08f64d7a825..d1f777945680 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -825,6 +825,10 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
.msi_capable = true,
.msix_capable = false,
.align = SZ_4K,
+ .bar[BAR_0] = { .only_64bit = true, },
+ .bar[BAR_1] = { .type = BAR_RESERVED, },
+ .bar[BAR_2] = { .only_64bit = true, },
+ .bar[BAR_3] = { .type = BAR_RESERVED, },
};
static const struct pci_epc_features *
@@ -933,6 +937,7 @@ static const struct of_device_id qcom_pcie_ep_match[] = {
{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
{ .compatible = "qcom,sdx55-pcie-ep", },
{ .compatible = "qcom,sm8450-pcie-ep", },
+ { .compatible = "qcom,sar2130p-pcie-ep", },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);