diff options
| author |   Jouni Högander <jouni.hogander@intel.com> | 2024-06-19 09:21:23 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-06-25 08:24:22 +0300 |
| commit | 67cf05473704e926d2b5302a68433a6aefde6fc5 (patch) | |
| tree | 4df9411ce907349ff4ba0b3ef965c046c698ed8f | |
| parent | drm/i915/psr: Inform Panel Replay source support on eDP as well (diff) | |
| download | wireguard-linux-67cf05473704e926d2b5302a68433a6aefde6fc5.tar.xz wireguard-linux-67cf05473704e926d2b5302a68433a6aefde6fc5.zip | |
drm/i915/psr: enable sink for eDP1.5 Panel Replay
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
v3:
- set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2
- PANEL_REPLAY_CONFIG2 is available in DP2.1 as well
v2: do not configure ALPM for DP2.0 Panel Replay
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-4-jouni.hogander@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 36 |
1 files changed, 30 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f4626699a37e..253888c7ea1d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -713,6 +713,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp, DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; + u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; if (crtc_state->has_sel_update) val |= DP_PANEL_REPLAY_SU_ENABLE; @@ -720,7 +721,14 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp, if (crtc_state->enable_psr2_su_region_et) val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; + if (crtc_state->req_psr2_sdp_prior_scanline) + panel_replay_config2 |= + DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); + + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, + panel_replay_config2); } static void _psr_enable_sink(struct intel_dp *intel_dp, @@ -751,15 +759,31 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); } +static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + u8 val; + + /* + * eDP Panel Replay uses always ALPM + * PSR2 uses ALPM but PSR1 doesn't + */ + if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay && + !crtc_state->has_sel_update)) + return; + + val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; + + if (crtc_state->has_panel_replay) + val |= DP_ALPM_MODE_AUX_LESS; + + drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); +} + void intel_psr_enable_sink(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - /* Enable ALPM at sink for psr2 */ - if (!crtc_state->has_panel_replay && crtc_state->has_sel_update) - drm_dp_dpcd_writeb(&intel_dp->aux, - DP_RECEIVER_ALPM_CONFIG, - DP_ALPM_ENABLE | - DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); + intel_psr_enable_sink_alpm(intel_dp, crtc_state); crtc_state->has_panel_replay ? _panel_replay_enable_sink(intel_dp, crtc_state) : |