diff options
| author |   Matthew Gerlach <matthew.gerlach@linux.intel.com> | 2025-02-21 11:04:51 -0600 |
|---|---|---|
| committer |   Krzysztof Wilczyński <kwilczynski@kernel.org> | 2025-03-05 22:22:08 +0000 |
| commit | 6843f38e16b96b072d0f576bf7cddde8cc5a103a (patch) | |
| tree | f1db6a8655e552cf4d67897a39d60959a54e277b | |
| parent | Linux 6.14-rc1 (diff) | |
| download | wireguard-linux-6843f38e16b96b072d0f576bf7cddde8cc5a103a.tar.xz wireguard-linux-6843f38e16b96b072d0f576bf7cddde8cc5a103a.zip | |
dt-bindings: PCI: altera: Add binding for Agilex
Add the compatible bindings for the three variants of the Agilex
PCIe Hard IP.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250221170452.875419-2-matthew.gerlach@linux.intel.com
[kwilczynski: update description within devicetree bindings]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index 52533fccc134..5d3f48a001b7 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,19 @@ maintainers: properties: compatible: + description: Each family of socfpga has its own implementation of the + PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported by the + altr,pcie-root-port-2.0. The Agilex family of chips has three, + non-register compatible, variants of PCIe Hard IP referred to as the + F-Tile, P-Tile, and R-Tile, depending on the specific chip instance. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: |