diff options
| author |   Jouni Högander <jouni.hogander@intel.com> | 2025-01-09 12:35:30 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-01-21 11:55:34 +0200 |
| commit | 68f3a505b367656a2db05406a62dc43fb0c50034 (patch) | |
| tree | 760fb2de98ae36cb6df43048364e88de40445063 | |
| parent | drm/i915/psr: Add new function for writing sink panel replay enable bit (diff) | |
| download | wireguard-linux-68f3a505b367656a2db05406a62dc43fb0c50034.tar.xz wireguard-linux-68f3a505b367656a2db05406a62dc43fb0c50034.zip | |
drm/i915/psr: Enable Panel Replay on sink always when it's supported
Currently we are configuring Panel Replay on sink when it get's
enabled. This means we need to do full modeset when enabling Panel
Replay. This is required as DP specification is saying sink Panel Replay
needs to be configured before link training. Avoid full modeset by enabling
Panel Replay on sink always when it's supported by the sink and the
source.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250109103532.2093356-3-jouni.hogander@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index acb986bc1f33..3693b36b9336 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2927,8 +2927,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state); /* Panel replay has to be enabled in sink dpcd before link training. */ - if (crtc_state->has_panel_replay) - intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); + intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); if (DISPLAY_VER(display) >= 14) mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); |