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| author |   Harry Austen <hpausten@protonmail.com> | 2024-09-13 19:11:37 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-10-09 16:38:56 -0700 |
| commit | 698a3e3c5ee6b2f91f3813a36a3b2f9ac0ec981b (patch) | |
| tree | b3f5ff668394df00fd1b45968d45bc0d7b8d7b24 | |
| parent | clk: clocking-wizard: move clock registration to separate function (diff) | |
| download | wireguard-linux-698a3e3c5ee6b2f91f3813a36a3b2f9ac0ec981b.tar.xz wireguard-linux-698a3e3c5ee6b2f91f3813a36a3b2f9ac0ec981b.zip | |
dt-bindings: clock: xilinx: describe whether dynamic reconfig is enabled
Xilinx clocking wizard IP core's dynamic reconfiguration support is
optionally enabled at build time. Add a devicetree boolean property to
describe whether the hardware supports this feature or not.
Since dynamic reconfiguration support was previously assumed enabled,
introduce a property to indicate the inverse, in order to maintain
devicetree backwards compatibility. Hence, this new xlnx,static-config
property should be specified when dynamic reconfiguration support is
disabled in the IP core configuration.
Signed-off-by: Harry Austen <hpausten@protonmail.com>
Link: https://lore.kernel.org/r/20240913191037.2690-6-hpausten@protonmail.com
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index 9d5324dc1027..b44a76a958f4 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -39,6 +39,11 @@ properties: - const: clk_in1 - const: s_axi_aclk + xlnx,static-config: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicate whether the core has been configured without support for dynamic + runtime reconfguration of the clocking primitive MMCM/PLL. xlnx,speed-grade: $ref: /schemas/types.yaml#/definitions/uint32 @@ -70,6 +75,7 @@ examples: compatible = "xlnx,clocking-wizard"; reg = <0xb0000000 0x10000>; #clock-cells = <1>; + xlnx,static-config; xlnx,speed-grade = <1>; xlnx,nr-outputs = <6>; clock-names = "clk_in1", "s_axi_aclk"; |