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author | 2021-03-16 09:06:44 +0100 | |
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committer | 2021-04-01 11:41:00 +0200 | |
commit | 6ed9269265e10669d62280a869652dbe26f43ecb (patch) | |
tree | 9107626c4d33b8e7f93d849c1f49a32720fd3307 | |
parent | ARM: dts: stm32: Enable crc1 and cryp1 where applicable on DHSOM (diff) | |
download | wireguard-linux-6ed9269265e10669d62280a869652dbe26f43ecb.tar.xz wireguard-linux-6ed9269265e10669d62280a869652dbe26f43ecb.zip |
ARM: dts: stm32: Add PTP clock to Ethernet controller
Add the PTP clock to the Ethernet controller. Otherwise, the driver uses the
main clock to derive the PTP frequency which is not necessarily the correct one.
Tested with linuxptp on Olimex STMP1-OLinuXino-LIME2.
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
-rw-r--r-- | arch/arm/boot/dts/stm32mp151.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 31b04485cbd7..fb80d53e6be2 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1425,11 +1425,13 @@ "mac-clk-tx", "mac-clk-rx", "eth-ck", + "ptp_ref", "ethstp"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, <&rcc ETHSTP>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; |