diff options
| author |   Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-10-27 14:11:08 +0100 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2022-10-28 21:48:31 -0700 |
| commit | 6f38fffe2179dd29612aea2c67c46ed6682b4e46 (patch) | |
| tree | 4b4add1ea507f52d30e13439d0c8ced449b54456 | |
| parent | net: mtk_eth_soc: add out of band forcing of speed and duplex in pcs_link_up (diff) | |
| download | wireguard-linux-6f38fffe2179dd29612aea2c67c46ed6682b4e46.tar.xz wireguard-linux-6f38fffe2179dd29612aea2c67c46ed6682b4e46.zip | |
net: mtk_eth_soc: move PHY power up
The PHY power up is common to both configuration paths, so move it into
the parent function. We need to do this for all serdes modes.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c index d26a0ba2e47b..63b25574caac 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -45,9 +45,6 @@ static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, SGMII_AN_RESTART, SGMII_AN_RESTART); - - regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, - SGMII_PHYA_PWD, 0); } /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a @@ -72,10 +69,6 @@ static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, SGMII_IF_MODE_MASK & ~SGMII_DUPLEX_FULL, SGMII_SPEED_1000); - - /* Release PHYA power down state */ - regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, - SGMII_PHYA_PWD, 0); } static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, @@ -91,6 +84,10 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, else if (phylink_autoneg_inband(mode)) mtk_pcs_setup_mode_an(mpcs); + /* Release PHYA power down state */ + regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, + SGMII_PHYA_PWD, 0); + return 0; } |