diff options
| author |   Andrew F. Davis <afd@ti.com> | 2017-12-12 16:43:06 -0600 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-12-13 12:27:48 +0000 |
| commit | 77bdb58795d86262e96ba37524489ba0969de253 (patch) | |
| tree | fb0c1a58198d843ffeb98ededc381a969819889f | |
| parent | ASoC: tlv320aic32x4: Use correct shift definition for DATATYPE bits (diff) | |
| download | wireguard-linux-77bdb58795d86262e96ba37524489ba0969de253.tar.xz wireguard-linux-77bdb58795d86262e96ba37524489ba0969de253.zip | |
ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits
Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/tlv320aic32x4.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 8f9719e6cdfd..9f643199e1ba 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -738,15 +738,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, data = data & ~(3 << 4); switch (params_width(params)) { case 16: + data |= (AIC32X4_WORD_LEN_16BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 20: - data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_20BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 24: - data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_24BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 32: - data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_32BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; } snd_soc_write(codec, AIC32X4_IFACE1, data); |