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| author |   Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-02-04 14:40:04 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-02-06 11:57:52 +0100 |
| commit | 79982cbac896768c3860c241df2028c3e75f5a6b (patch) | |
| tree | fe837eecdc1c1056d9843881d36c69a59423e6bf | |
| parent | dt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588 HDMI TX Controller (diff) | |
| download | wireguard-linux-79982cbac896768c3860c241df2028c3e75f5a6b.tar.xz wireguard-linux-79982cbac896768c3860c241df2028c3e75f5a6b.zip | |
dt-bindings: display: vop2: Add optional PLL clock properties
On RK3588, HDMI PHY PLL can be used as an alternative and more accurate
pixel clock source for VOP2 video ports 0, 1 and 2.
Document the optional PLL clock properties corresponding to the two HDMI
PHYs available on the SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20250204-vop2-hdmi0-disp-modes-v3-1-d71c6a196e58@collabora.com
| -rw-r--r-- | Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml index 2531726af306..46d956e63338 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -53,6 +53,8 @@ properties: - description: Pixel clock for video port 2. - description: Pixel clock for video port 3. - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY PLL. + - description: Alternative pixel clock provided by HDMI1 PHY PLL. clock-names: minItems: 5 @@ -64,6 +66,8 @@ properties: - const: dclk_vp2 - const: dclk_vp3 - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle |