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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2024-05-27 15:15:41 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-03 09:46:18 +0200 |
| commit | 7c8730df594e32d46d6728c07f89ea75c5e6a71d (patch) | |
| tree | da61e438325d88c1871128fe293f1ea98dd79da0 | |
| parent | clk: renesas: r8a779h0: Add ISPCS clocks (diff) | |
| download | wireguard-linux-7c8730df594e32d46d6728c07f89ea75c5e6a71d.tar.xz wireguard-linux-7c8730df594e32d46d6728c07f89ea75c5e6a71d.zip | |
clk: renesas: r8a779h0: Add CSI-2 clocks
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2
interfaces on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r8a779h0-cpg-mssr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index c9bea479a18e..034e375f31fe 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), |