diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-17 01:12:47 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 10:52:21 +0100 |
| commit | 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 (patch) | |
| tree | 9070c677278a38aa95e7d8caf79b8b96f8198020 | |
| parent | arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes (diff) | |
| download | wireguard-linux-7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2.tar.xz wireguard-linux-7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2.zip | |
arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board. This patch adds pinmux and spi1 nodes to the carrier
board dtsi file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117011247.27621-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 4c32f068a1f0..6f2a8bdfa225 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -263,6 +263,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ + <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ + <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ + <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ + }; + ssi0_pins: ssi0 { pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ @@ -318,6 +325,13 @@ status = "okay"; }; +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &ssi0 { pinctrl-0 = <&ssi0_pins>; pinctrl-names = "default"; |