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| author |   Likun Gao <Likun.Gao@amd.com> | 2020-04-09 15:33:53 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:12 -0400 |
| commit | 80c36f8646ebf0018e3e8bb5de35f7e7be664f54 (patch) | |
| tree | 07028b803db197497a9d22d4ea9d397cf7a62d4c | |
| parent | drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encode (diff) | |
| download | wireguard-linux-80c36f8646ebf0018e3e8bb5de35f7e7be664f54.tar.xz wireguard-linux-80c36f8646ebf0018e3e8bb5de35f7e7be664f54.zip | |
drm/amd/powerplay: enable ULCK DS for sienna_cichlid
Enable uclk deep sleep for sienna_cichlid.
Df cstate kicks in first, then df triggers uclk ds with the sideband.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 545b4efc2bfa..8e3fe192e50a 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -301,6 +301,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_FCLK_BIT) + | FEATURE_MASK(FEATURE_DS_UCLK_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) |