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| author |   David Galiffi <David.Galiffi@amd.com> | 2020-06-11 17:36:14 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:26 -0400 |
| commit | 8582aea20bc5de1fc4f2029e6cde604b2c755c0a (patch) | |
| tree | 216e3834806481813dfd5286bd851dac3c4b3a87 | |
| parent | drm/amd/display: enable seamless boot for dcn30 (diff) | |
| download | wireguard-linux-8582aea20bc5de1fc4f2029e6cde604b2c755c0a.tar.xz wireguard-linux-8582aea20bc5de1fc4f2029e6cde604b2c755c0a.zip | |
drm/amd/display: Compare v_front_porch when checking if streams are synchronizable
[Why]
If the front porch of the two timings differ, then there may not be
enough time while both streams are in vertical blank to perform a memory
clock change. This can hang the system.
[How]
Check the each streams timing.v_front_porch when determining if the two
streams are synchronizable.
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 3d0003c69373..1000dc6daf72 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -399,6 +399,10 @@ bool resource_are_streams_timing_synchronizable( != stream2->timing.v_addressable) return false; + if (stream1->timing.v_front_porch + != stream2->timing.v_front_porch) + return false; + if (stream1->timing.pix_clk_100hz != stream2->timing.pix_clk_100hz) return false; |