diff options
| author |   Siddharth Vadapalli <s-vadapalli@ti.com> | 2025-02-09 13:47:33 +0530 |
|---|---|---|
| committer |   Vignesh Raghavendra <vigneshr@ti.com> | 2025-03-02 18:43:33 +0530 |
| commit | 871c73229bd276fbdb43c42fb3f5a25bcd8a9c85 (patch) | |
| tree | 05c9303c1b705f386785eb60e9b700f72fa10a39 | |
| parent | arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3 (diff) | |
| download | wireguard-linux-871c73229bd276fbdb43c42fb3f5a25bcd8a9c85.tar.xz wireguard-linux-871c73229bd276fbdb43c42fb3f5a25bcd8a9c85.zip | |
arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3
The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-SK is connected to USB0 via
SERDES3, supporting USB DFU boot requires SERDES3 link associated with
USB0 to be functional at all stages of the USB DFU boot process. Thus,
add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250209081738.1874749-3-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 69b3d1ed8a21..440ef57be294 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1040,6 +1040,7 @@ #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_USB3>; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; |