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| author |   Michael Ellerman <mpe@ellerman.id.au> | 2024-12-18 21:54:50 +1100 |
|---|---|---|
| committer |   Madhavan Srinivasan <maddy@linux.ibm.com> | 2025-02-26 21:15:07 +0530 |
| commit | 8e4f1a3495c2f22ad01bb4c925950d680bbbe5aa (patch) | |
| tree | 8f27bbd1fdff61c686a5d9ec02f423ae2984d2e6 | |
| parent | powerpc/cell: Remove support for IBM Cell Blades (diff) | |
| download | wireguard-linux-8e4f1a3495c2f22ad01bb4c925950d680bbbe5aa.tar.xz wireguard-linux-8e4f1a3495c2f22ad01bb4c925950d680bbbe5aa.zip | |
powerpc: Remove some Cell leftovers
Now that CONFIG_PPC_CELL_NATIVE is removed, iommu_fixed_is_weak will
always be false, so remove it entirely.
Also remove a hack/quirk in the HTAB code that was only used on Cell.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20241218105523.416573-2-mpe@ellerman.id.au
| -rw-r--r-- | arch/powerpc/include/asm/iommu.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/kernel/dma-iommu.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/mm/book3s64/hash_utils.c | 12 |
3 files changed, 1 insertions, 19 deletions
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index 04072b5f8962..b410021ad4c6 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h @@ -317,12 +317,6 @@ extern void iommu_flush_tce(struct iommu_table *tbl); extern enum dma_data_direction iommu_tce_direction(unsigned long tce); extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir); -#ifdef CONFIG_PPC_CELL_NATIVE -extern bool iommu_fixed_is_weak; -#else -#define iommu_fixed_is_weak false -#endif - extern const struct dma_map_ops dma_iommu_ops; #endif /* __KERNEL__ */ diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index f0ae39e77e37..4d64a5db50f3 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c @@ -136,7 +136,7 @@ static bool dma_iommu_bypass_supported(struct device *dev, u64 mask) struct pci_dev *pdev = to_pci_dev(dev); struct pci_controller *phb = pci_bus_to_host(pdev->bus); - if (iommu_fixed_is_weak || !phb->controller_ops.iommu_bypass_supported) + if (!phb->controller_ops.iommu_bypass_supported) return false; return phb->controller_ops.iommu_bypass_supported(pdev, mask); } diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c index c8b4fa71d4a7..734610052cf4 100644 --- a/arch/powerpc/mm/book3s64/hash_utils.c +++ b/arch/powerpc/mm/book3s64/hash_utils.c @@ -1358,18 +1358,6 @@ static void __init htab_initialize(void) } else { unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; -#ifdef CONFIG_PPC_CELL - /* - * Cell may require the hash table down low when using the - * Axon IOMMU in order to fit the dynamic region over it, see - * comments in cell/iommu.c - */ - if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { - limit = 0x80000000; - pr_info("Hash table forced below 2G for Axon IOMMU\n"); - } -#endif /* CONFIG_PPC_CELL */ - table = memblock_phys_alloc_range(htab_size_bytes, htab_size_bytes, 0, limit); |