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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-15 18:59:27 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:06 +0100 |
| commit | 90a2bee8a0c2889617d39e637547aa4728fcb43d (patch) | |
| tree | 3e02f965b1269c1219474232fb7a6a00f6383983 | |
| parent | clk: renesas: r8a779h0: Add FCPVX clock (diff) | |
| download | wireguard-linux-90a2bee8a0c2889617d39e637547aa4728fcb43d.tar.xz wireguard-linux-90a2bee8a0c2889617d39e637547aa4728fcb43d.zip | |
clk: renesas: r8a779h0: Add VSPX clock
Add the VSPX modules clock for Renesas R-Car V4M.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115175927.3714357-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 9dc70a5e55f6..ffea06d77d5e 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D1_VIO), DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D1_VIO), DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), |